參數(shù)資料
型號(hào)： TLV320AIC23BGQER
廠商： Texas Instruments, Inc.
元件分類： Codec
英文描述： STEREO AUDIO CODEC 8 TO 96 KHZ WITH INTEGRATED HEADPHONE AMPLIFIER
中文描述： 立體聲音頻編解碼8至96與集成耳機(jī)放大器KHZ可
文件頁數(shù)： 25/50頁
文件大?。?/td> 499K
代理商： TLV320AIC23BGQER
35
Sample Rate Control (Address: 0001000)
BIT
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
X
CLKOUT
CLKIN
SR3
SR2
SR1
SR0
BOSR
USB/Normal
Default
0
0
0
1
0
0
0
0
0
CLKIN
CLKOUT
SR[3:0]
BOSR
Clock input divider
Clock output divider
Sampling rate control (see Sections 3.3.2.1 AND 3.3.2.2)
Base oversampling rate
USB mode:
0 = 250 f
s
Normal mode:
0 = 256 f
s
Clock mode select:
0 = Normal
Reserved
Digital Interface Activation (Address: 0001001)
0 = MCLK
0 = MCLK
1 = MCLK/2
1 = MCLK/2
1 = 272 f
s
1 = 384 f
s
1 = USB
USB/Normal
X
BIT
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
X
RES
RES
X
X
X
X
X
ACT
Default
0
0
0
0
0
0
0
0
0
ACT
X
Reset Register (Address: 0001111)
Activate interface
Reserved
0 = Inactive
1 = Active
BIT
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
RES
RES
RES
RES
RES
RES
RES
RES
RES
Default
0
0
0
0
0
0
0
0
0
RES
Write 000000000 to this register triggers reset
3.2
Analog Interface
3.2.1
Line Inputs
The TLV320AIC23B has line inputs for the left and the right audio channels (RLINEIN and LLINEIN). Both line inputs
have independently programmable volume controls and mutes. Active and passive filters for the two channels
prevent high frequencies from folding back into the audio band.
The line-input gain is logarithmically adjustable from 12 dB to –34.5 dB in 1.5-dB steps. The ADC full-scale range
is 1.0 V
RMS
at AV
DD
= 3.3 V. The full-scale range tracks linearly with analog supply voltage AV
DD
. To avoid distortions,
it is important not to exceed the full-scale range.
The gain is independently programmable on both left and right line-inputs. To reduce the number of software write
cycles required. Both channels can be locked to the same value by setting the RLS and LRS bits (see Section 3.1.3).
The line inputs are biased internally to VMID. When the line inputs are muted or the device is set to standby mode,
the line inputs are kept biased to VMID using special antithump circuitry. This reduces audible clicks that otherwise
might be heard when reactivating the inputs.
For interfacing to a CD system, the line input should be scaled to 1 V
RMS
to avoid clipping, using the circuit shown
in Figure 3-3.
R
2
R1
C1
C2
+
CDIN
LINEIN
AGND
Figure 33. Analog Line Input Circuit
Where:
R1 = 5 k
R2 = 5 k
C1 = 47 pF
C2 = 470 nF
R1 and R2 divide the input signal by two, reducing the 2 V
RMS
from the CD player to the nominal 1 V
RMS
of the AIC23B
inputs. C1 filters high-frequency noise, and C2 removes any dc component from the signal.
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