參數(shù)資料
型號: TLV320AIC23BGQER
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: STEREO AUDIO CODEC 8 TO 96 KHZ WITH INTEGRATED HEADPHONE AMPLIFIER
中文描述: 立體聲音頻編解碼8至96與集成耳機(jī)放大器KHZ可
文件頁數(shù): 21/50頁
文件大?。?/td> 499K
代理商: TLV320AIC23BGQER
31
3 How to Use the TLV320AIC23B
3.1
Control Interfaces
The TLV320AIC23B has many programmable features. The control interface is used to program the registers of the
device. The control interface complies with SPI (three-wire operation) and two-wire operation specifications. The
state of the MODE terminal selects the control interface type. The MODE pin must be hardwired to the required level.
MODE
INTERFACE
0
2-wire
1
SPI
3.1.1
SPI
In SPI mode, SDIN carries the serial data, SCLK is the serial clock and CS latches the data word into the
TLV320AIC23B. The interface is compatible with microcontrollers and DSPs with an SPI interface.
A control word consists of 16 bits, starting with the MSB. The data bits are latched on the rising edge of SCLK. A rising
edge on CS after the 16th rising clock edge latches the data word into the AIC (see Figure 3-1).
The control word is divided into two parts. The first part is the address block, the second part is the data block:
B[15:9]
B[8:0]
Control Address Bits
Control Data Bits
B15 B14 B13 B12 B11 B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
MSB
LSB
CS
SCLK
SDIN
Figure 31. SPI Timing
3.1.2
2-Wire
In 2-wire mode, the data transfer uses SDIN for the serial data and SCLK for the serial clock. The start condition is
a falling edge on SDIN while SCLK is high. The seven bits following the start condition determine which device on
the 2-wire bus receives the data. R/W determines the direction of the data transfer. The TLV320AIC23B is a write only
device and responds only if R/W is 0. The device operates only as a slave device whose address is selected by setting
the state of the CS pin as follows.
CS STATE
(Default = 0)
ADDRESS
0
0011010
1
0011011
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