參數(shù)資料
型號(hào): TLV320AIC23BGQER
廠商: Texas Instruments, Inc.
元件分類(lèi): Codec
英文描述: STEREO AUDIO CODEC 8 TO 96 KHZ WITH INTEGRATED HEADPHONE AMPLIFIER
中文描述: 立體聲音頻編解碼8至96與集成耳機(jī)放大器KHZ可
文件頁(yè)數(shù): 22/50頁(yè)
文件大?。?/td> 499K
代理商: TLV320AIC23BGQER
32
The device that recognizes the address responds by pulling SDIN low during the ninth clock cycle, acknowledging
the data transfer. The control follows in the next two eight-bit blocks. The stop condition after the data transfer is a
rising edge on SDIN when SCLK is high (see Figure 3-2).
The 16-bit control word is divided into two parts. The first part is the address block, the second part is the data block:
B[15:9]
B[8:0]
Control Address Bits
Control Data Bits
SCLK
SDI
ADDR
R/W ACK B15 B8 ACK
B7 B0 ACK
Start
Stop
1
7
8
9
1
8
9
1
8
9
Figure 32. 2-Wire Compatible Timing
3.1.3
Register Map
The TLV320AIC23B has the following set of registers, which are used to program the modes of operation.
ADDRESS
REGISTER
0000000
Left line input channel volume control
0000001
Right line input channel volume control
0000010
Left channel headphone volume control
0000011
Right channel headphone volume control
0000100
Analog audio path control
0000101
Digital audio path control
0000110
Power down control
0000111
Digital audio interface format
0001000
Sample rate control
0001001
Digital interface activation
0001111
Reset register
Left line input channel volume control (Address: 0000000)
BIT
D8
D7
D6
D5
D4
D3
D2
D1
D0
Function
LRS
LIM
X
X
LIV4
LIV3
LIV2
LIV1
LIV0
Default
0
1
0
0
1
0
1
1
1
LRS
Left/right line simultaneous volume/mute update
Simultaneous update
Left line input mute
Left line input volume control (10111 = 0 dB default)
11111 = +12 dB down to 00000 = –34.5 dB in 1.5-dB steps
Reserved
0 = Disabled
0 = Normal
1 = Enabled
1 = Muted
LIM
LIV[4:0]
X
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