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參數(shù)資料
| 型號： | TLV320AD11A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | 3.3 V INTEGRATED ADSL OVER POTS CODEC |
| 中文描述： | 3.3伏集成ADSL POTS和編解碼器 |
| 文件頁數(shù)： | 6/28頁 |
| 文件大?。?/td> | 412K |
| 代理商： | TLV320AD11A |
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TLV320AD11A
3.3 V INTEGRATED ADSL OVER POTS CODEC
SLWS087B – JUNE 1999 – REVISED MARCH 2000
6
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
communication channels
transmitter channel/echo-cancellation channel
The transmitter channel is powered by a high performance DAC. This is a 4.416-MHz, 14-bit DAC that provides a
16X over-sampling to reduce DAC noise. The input buffer is sampled at either 276 KSPS (pin OSEN = low,
default), or 552 KSPS (pin OSEN = high). A low-pass filter limits its output to 138 kHz. A programmable
attenuator, with a range between 0 and –24 dB in –1-dB steps, drives the output into the external ADSL line
driver.
A second transmitter is used to perform pre-echo cancellation. This analog echo cancellation helps reduce the
dynamic range requirements of the RT receiver. It has the same function as the first transmitter channel. It drives
a separate external line driver to perform the cancellation.
receiver channel
The receiver channel has two PGAs and an equalizer to match the loop loss and flatten the spectrum. This
results in a reduction in dynamic range requirement for the high resolution ADC. The receiver channel also has a
1.104-MHz low-pass filter with a 4.416 MSPS and a 14-bit ADC to provide a 2X over-sampling. The output buffer
is updated at either 2208 KSPS (pin OSEN = low, default), or 4416 KSPS (pin OSEN = high).
VCXO-control DAC
A 12-bit DAC is used to control the external 35.328-MHz VCXO (voltage control oscillator) that provides the
system clock to the codec. In a typical application, the typical update rate of the DAC is about 4 kHz, depending
on the ADSL frame rate. The host DSP initiates the update through the serial interface. The two 8-bit registers
SCR4 and SCR5 (each 2s complement) are used to generate the 12-bit code for the DAC. This requires the
use of 16 bits to obtain a 12-bit number. So the lower 4 bits of the MSB register (SCR5[3:0]) are added (2s
complement) to the higher 4 bits of the LSB register (SCR4[7:4]). Refer to Figure 1 for code generation. The
updated code is sent to the DAC two SCLKs after the SCR4 register is received. Notice that if SCR5 does not
need to be updated, only one write cycle to SCR4 is needed to update the VCXO DAC. In this case, the lower
8 bits of the 12-bit word will be updated.
12-bit code for VCXO DAC
D7
D7
D7
D7
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SCR4
SCR5
+
Figure 1. 12-Bit Code Generation for VCXO DAC
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