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參數(shù)資料
| 型號： | TLV320AD11A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | 3.3 V INTEGRATED ADSL OVER POTS CODEC |
| 中文描述： | 3.3伏集成ADSL POTS和編解碼器 |
| 文件頁數(shù)： | 20/28頁 |
| 文件大?。?/td> | 412K |
| 代理商： | TLV320AD11A |
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TLV320AD11A
3.3 V INTEGRATED ADSL OVER POTS CODEC
SLWS087B – JUNE 1999 – REVISED MARCH 2000
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
parallel port (see Figures 2, 3, and 4)
PARAMETER
MIN
TYP
MAX
UNIT
tc1
Period, CLKIN
28.3
ns
t2
tc2
Cycle time INT
Cycle time, INT
OSEN=0
16
OSEN=1
8
CLKIN
tc3
td1
td2
td3
td4
td5
td6
Period, CLKOUT
Delay time, keep-out zone end to INT
↑
Delay time, keep-out zone end (CLKIN
↑
) to OE
↓
/CS
↓
8
5
ns
0
ns
Delay time, keep-out zone end to WETX
↓
/CS
↓
or WEEC
↓
/CS
↓
0
ns
Delay time, data valid after OE
↓
/CS
↓
Delay time, data becomes Hi-Z after OE
↑
/CS
↑
15
ns
5
ns
Delay time, keep-out zone end to SCLK/READY
↑
14.2
ns
td7
Delay time, SCLK/READY
↓
to keep-out zone
14.2
ns
td9
th1
th2
th3
tsu1
tsu2
tsu3
tw1
tw2
tw3
tw4
tw5
Delay time, time between the rising edge of WETX/WEEC to the rising edge of CS
5
ns
Hold time, data valid after WETX
↑
Hold time, data valid after WEEC
↑
Hold time, SYNC keep high after CLKIN
↑
Setup time, data valid before WETX
↑
Setup time, data valid before WEEC
↑
or second WETX
↑
Setup time, SYNC is high before CLKIN
↑
Pulse width, keep-out zone time
5
ns
5
ns
5
ns
15
ns
15
ns
10
ns
1
CLKIN
Pulse width, OE
20
ns
Pulse width, WETX or WETX first pulse
28
ns
Pulse width, WEEC or WETX second pulse
28
ns
Pulse width, SYNC
28
ns
serial port (see Figure 6)
PARAMETER
MIN
TYP
MAX
UNIT
tc4
Cycle time, SCLK
8
CLKIN
td8
th4
th5
tsu4
tsu5
tw6
Delay time, SCLK rising edge to SDO valid
15
ns
Hold time, FS keep high after SCLK
↓
SDI valid after SCLK
↓
Setup time, FS valid before SCLK
↓
SDI valid before SCLK
↓
5
ns
5
ns
20
ns
20
ns
FS pulse width
28
ns
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