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參數(shù)資料
| 型號： | TLV320AD11A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | 3.3 V INTEGRATED ADSL OVER POTS CODEC |
| 中文描述： | 3.3伏集成ADSL POTS和編解碼器 |
| 文件頁數(shù)： | 17/28頁 |
| 文件大?。?/td> | 412K |
| 代理商： | TLV320AD11A |
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TLV320AD11A
3.3 V INTEGRATED ADSL OVER POTS CODEC
SLWS087B – JUNE 1999 – REVISED MARCH 2000
17
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, AVDD to AGND, DVDD to DGND
Analog input voltage range to AGND
Digital input voltage range to DGND
Operating
virtual junction temperature range, T
J
Operating
free-air temperature range, T
A
Storage temperature range, T
str
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
–0.3 V to 4.5 V
–0.3 V to AVDD+0.3 V
–0.3 V to DVDD+0.3 V
–40
°
C to 150
°
C
–40
°
C to 85
°
C
–65
°
C to 150
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
260
°
C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
recommended operating conditions
power supply
MIN
NOM
MAX
UNIT
Supply voltage
AVDD_FIL_TX, AVDD_FIL_EC, AVDD1_TX, AVDD2_TX, AVDD1_EC, AVDD2_EC;
AVDD_FIL_RX, AVDD_ADC;
AVDD_REF
3
3.3
3.6
V
DVDD_BF, DVDD_CLK, DVDD_LG, DVDD_RX, DVDD_DAC
3
3.3
3.6
digital inputs
MIN
NOM
MAX
UNIT
High-level input voltage, VIH
Low-level input voltage, VIL
II = 0.75 mA
II = –0.75 mA
2
V
0.8
analog input
MIN
AVDD_FIL_RX/2
±
0.75
3
NOM
MAX
UNIT
V
Analog input signal range
AVDD_FIL_RX = 3.3 V. The input signal is measured single-ended.
AVDD_FIL_RX = 3.3 V. The input signal is measured differentially.
Vp–p
clock inputs
MIN
NOM
35.328
MAX
UNIT
MHz
Input clock frequency
DVDD CLK=3 3 V
DVDD_CLK=3.3 V
Input clock duty cycle
50%
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