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參數(shù)資料
| 型號： | TLV320AD11A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | 3.3 V INTEGRATED ADSL OVER POTS CODEC |
| 中文描述： | 3.3伏集成ADSL POTS和編解碼器 |
| 文件頁數(shù)： | 16/28頁 |
| 文件大?。?/td> | 412K |
| 代理商： | TLV320AD11A |
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TLV320AD11A
3.3 V INTEGRATED ADSL OVER POTS CODEC
SLWS087B – JUNE 1999 – REVISED MARCH 2000
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
register programming (continued)
SCR13 – EC channel digital gain control register Address:1101b
Contents at reset: 00000000b
SCR13 has the same format as SCR11. Check with SCR11 for details.
SCR14 – Miscellaneous control register 2
Address:1110b
Contents at reset: 00000000b
D7
D6
D5
D4
D3
D2
D1
D0
REGISTER
VALUE (HEX)
DESCRIPTION
0
0
0
0
–
–
–
1
One write operation reset. (see Note 9)
0
0
0
0
–
–
1
–
Enable FIFO
0
0
0
0
–
1
–
–
Bypass EC DHPF (25.875 kHz)
0
0
0
0
1
–
–
–
ECP and ECM are connected to weakly driven mid-supply. It can only be
used during EC power-down mode.
NOTE 9: Write-synchronized operation: A 1 is written to bit D0 of SCR14 register after pin ONE_WE is set to high. This sets the start point for
the TX/EC operation. During the first WETX pulse, data is written to the TX channel. During the second WETX pulse, data is written
to the EC channel. D0 of SCR14 is always self-cleared; therefore, the read-back value of bit D0 of SCR14 is always zero.
device initialization time
The TLV320AD11A completes all calibration and initialization in less than 1 second. This includes reference
settling time (
≈
950
μ
s), one rest after power up (1 serial frame), VCXODAC configuration (2 serial frames),
TX/RX gain select (4 serial frames), and self-calibration of the DAC (256X113 ns). Each 16-bit frame requires
up to 5
μ
s. The host processor needs to initiate this process upon a successful power up.
power-down
Both hardware and software power-down modes are provided. The serial interface is operative when the codec
is in power-down mode. By sending commands through serial interface, either the codec or part of the codec,
can be software powered down. All the references are kept on in the software power-down mode. The codec
can also be hardware powered down by setting PWDN pin to high. All the references are shut off in the hardware
power-down mode. The contents of the registers will not change in either power-down modes.
power supply grouping recommendation
The following power supply grouping is recommended for best performance of this device. Ferrite beads are
used to separate group1, group 2, and group 3 if the same 3.3-V analog power source is shared
Group 1: AVDD_FIL_TX, AVDD_FIL_EC, AVDD1_TX, AVDD2_TX, AVDD1_EC, AVDD2_EC
Group 2: AVDD_FIL_RX, AVDD_ADC
Group 3: AVDD_REF
Group 4: DVDD_BF, DVDD_CLK, DVDD_LG, DVDD_RX, DVDD_DAC
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