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參數(shù)資料
| 型號： | TLV320AD11A |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | Codec |
| 英文描述： | 3.3 V INTEGRATED ADSL OVER POTS CODEC |
| 中文描述： | 3.3伏集成ADSL POTS和編解碼器 |
| 文件頁數(shù)： | 5/28頁 |
| 文件大?。?/td> | 412K |
| 代理商： | TLV320AD11A |
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TLV320AD11A
3.3 V INTEGRATED ADSL OVER POTS CODEC
SLWS087B – JUNE 1999 – REVISED MARCH 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions(Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
35
SDO
O
Serial data output
SYNC
45
I
SYNC pulse for clock synchronization. A high pulse to the pin synchronizes the clock operation. The
default state of the pin is low. Refer to Figure 4 for detail.
TXM
82
O
Transmit output minus
TXP
81
O
Transmit output plus
VCXOCNTL
59
O
VCXO DAC output
Decoupling 1.5 V for ADC. Add 10
μ
F tantalum and 0.1
μ
F ceramic capacitors to AVSS_ADC.
Decoupling 1.5 V reference voltage. Add 10
μ
F tantalum and 0.1
μ
F ceramic capacitors to AVSS_REF.
Substrate. VSS needs to connect to analog ground.
Write enable to EC channel from host processor, when ONE_WE (pin 98) is low. If ONE_WE is high, it
functions as second chip select, CS2, and both CS and CS2 need to be low in order to have WETX
access data on the parallel bus.
VMID_ADC
11
O
VMID_REF
90
O
VSS
WEEC/CS2
92
I
49
I
WETX
48
I
Write enable for TX channel from host processor. If ONE_WE is high, it functions as write enable for both
TX and EC after hardware reset or write to SCR14[0]. In this case, the first low-going pulse of WETX will
be a write to TX channel, and the second one will be a write to EC channel
functional block diagram
Input
Buffer
FS
SDI
SDO
SCLK
ADR1
ADR0
Parallel
Bus
Serial
Interface
PAA
CODEC
Interface
INTRP
2
×
276 KSPS
TX
DAC
14 Bit
4.416 MSPS
TX
LPF
138 kHz
TXP
TXM
0 to –24 dB
(–1 dB/step)
TX PAA
1.104 MHz
14 Bit
4.416 MSPS
PGA2
0 to 11.5 dB
(0.25 dB/step)
1.104 MHz
(25 dB Boost
5 dB/step)
PGA1
0 to 6 dB
(1 dB/step)
RXP
RXM
VCXO
DAC
VCXO
35.328 MHz
VCXOCNTL
CLKIN
Clock
Generator
CLKOUT
4.416 MHz
Internal
Reference
GP0–7
OSEN
Input
Buffer
Output
Buffer
Digital
LPF
INTRP
8
×
552
KSPS
138 kHz
4416
KSPS
PAA
INTRP
2
×
276 KSPS
EC
DAC
14 Bit
4.416 MSPS
EC
LPF
138 kHz
ECP
ECM
0 to –24 dB
(–1 dB/step)
EC PAA
OSEN
Digital
LPF
INTRP
8
×
552
KSPS
138 kHz
4416
KSPS
Digital
LPF
DEC/2
OSEN
RX
ADC
RX
LPF
2208
KSPS
4416
KSPS
4416
KSPS
RX
EQ
GP0–GP7
Control Block
SYNC
RESET
PWDN
CONFIG2
OE_SYNC
ONE_WE
WETX
INT
WEEC
OE
D0–D15
OSEN
D0–D15
Digital
HPF
25.875 kHz
SCR7[0]
Digital
HPF
25.875 kHz
SCR14[2]
4VPP
3VPP
D0–D15
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