參數(shù)資料
型號(hào): TLC320AD81CDBT
廠商: TEXAS INSTRUMENTS INC
元件分類: 音頻控制
英文描述: 2 CHANNEL(S), EQUALIZER CIRCUIT, PDSO38
封裝: PLASTIC, TSSOP-38
文件頁(yè)數(shù): 8/47頁(yè)
文件大?。?/td> 195K
代理商: TLC320AD81CDBT
2–4
2.7
Right-Justified Serial Format
MSB
X
SDIN1
SCLK
MSB
X
LSB
MSB
X
MSB
X
LSB
Left Channel
Right Channel
SDOUT
LRCLK = fs
Figure 2–3. Right-Justified Serial Format
2.7.1
Protocol
1.
LRCLK = Sampling frequency (fs)
2.
Left channel is transmitted when LRCLK is high
3.
The SDIN1 data is justified to the trailing edge of the LRCLK
4.
Serial data is sampled on the rising edge of SCLK
5.
Serial data is transmitted on the falling edge of SCLK
6.
SCLK = 64 LRCLK
7.
In this mode, LRCLK does not have to be a 50% duty cycle clock. The number of bits used in the
interface sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.
2.7.2
Implementation
1.
LRCLK and SCLK are both inputs
2.7.3
Timing
See Figure 4–1 for I2S timing.
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