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參數(shù)資料
| 型號： | TLC320AD81CDBT |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 音頻控制 |
| 英文描述： | 2 CHANNEL(S), EQUALIZER CIRCUIT, PDSO38 |
| 封裝： | PLASTIC, TSSOP-38 |
| 文件頁數(shù)： | 18/47頁 |
| 文件大小： | 195K |
| 代理商： | TLC320AD81CDBT |
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3–3
3.5
Audio Serial Port Timing Requirements (see Note 3)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
Frequency, SCLK
32 fs
64 fs
MHz
tr(SCLK)
Rise time, SCLK (see Note 4)
5
16.3
25
ns
tf(SCLK)
Fall time, SCLK (see Note 4)
5
16.3
25
ns
td(SLR)
Delay time, SCLK rising to LRCLK edge (see Note 5)
50
ns
td(SDOUT)
Delay time, SDOUT valid from SCLK falling
100
ns
tsu(SDIN)
Setup time, SDIN before SCLK rising edge
10
ns
th(SDIN)
Hold time, SDIN from SCLK rising edge
100
ns
Valid in 16-bit left justified mode only.
NOTES:
3. Timing relative to 256 fs MCLK.
4. SCLK rising and falling are measured from 20% to 80%.
5. The rising edge of SCLK must not occur at the same time as either edge of LRCLK.
3.6
I2C Serial Port Timing Requirements
PARAMETER
MIN
MAX
UNIT
f(scl)
SCL clock frequency
0
100
kHz
tBUF
Bus free time between start and stop
4.7
s
tw(low)
Pulse duration, SCL clock low (see Note 6)
4.7
s
tw(high)
Pulse duration, SCL clock high (see Note 7)
4
s
th(STA)
Hold time, repeated start
4
s
tsu(STA)
Setup time, repeated start
4.7
20
s
th(DAT)
Hold time, data
0
s
tsu(DAT)
Setup time, data
250
ns
tr
Rise time for SDA and SCL
1000
ns
tf
Fall time for SDA and SCL
300
ns
tsu(STO)
Setup time for stop condition
4
s
A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the
falling edge of SCL.
NOTES:
6. tw(low) is measured from the end of tf to the beginning of tr.
7. tw(high) is measured from the end of tr to the beginning of tf.
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