參數(shù)資料
型號: TLC320AD81C
廠商: Texas Instruments, Inc.
英文描述: Stereo Audio Digital Equalizer DC
中文描述: 立體聲音頻數(shù)字均衡器直流
文件頁數(shù): 36/47頁
文件大?。?/td> 185K
代理商: TLC320AD81C
6–2
MCLK
LRCLK
SDIN1
SCLK
TLC320AD81C
SCL
SDA
I2C
Controller
SPDIF
RECEIVER
Left
Right
SPDIF
Data
Figure 6–2. Example SPDIF Audio System
6.1
The TLC320AD81C handles three data lengths for received audio data. In 20-bit mode, the two least
significant bits are truncated to 18 bits before the data is processed. These 18 bits are available after
processing at the SDOUT pin. However, two more bits are truncated before the digital-to-analog (D/A)
conversion of the data, therefore 16-bit analog performance is seen at the analog output pins (Out_L and
Out_R). In 18-bit mode, all 18 bits are passed through or processed digitally. The 18 bits are available at
the SDOUT pin. Again two bits are truncated before the digital-to-analog conversion for 16-bit analog output
performance. In 16-bit mode, all 16 bits are passed through or processed both digitally and through D/A
conversion, but the 16 bits are shifted up two significant bit places before processing. Thus 18 bits are
available at SDOUT with 16 bits being data and the two least significant bits being padded zeros. The original
16 bits are passed through the D/A converter.
Audio Data
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