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參數(shù)資料
| 型號： | TLC320AD81C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Stereo Audio Digital Equalizer DC |
| 中文描述： | 立體聲音頻數(shù)字均衡器直流 |
| 文件頁數(shù)： | 25/47頁 |
| 文件大?。?/td> | 185K |
| 代理商： | TLC320AD81C |
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3–3
3.5
Audio Serial Port Timing Requirements (see Note 3)
PARAMETER
MIN
TYP
MAX
UNIT
f(SCLK)
tr(SCLK)
tf(SCLK)
td(SLR)
td(SDOUT)
tsu(SDIN)
th(SDIN)
Valid in 16-bit left justified mode only.
NOTES:
3. Timing relative to 256 fs MCLK.
4. SCLK rising and falling are measured from 20% to 80%.
5. The rising edge of SCLK must not occur at the same time as either edge of LRCLK.
I
2
C Serial Port Timing Requirements
Frequency, SCLK
32 fs
64 fs
MHz
Rise time, SCLK (see Note 4)
5
16.3
25
ns
Fall time, SCLK (see Note 4)
5
16.3
25
ns
Delay time, SCLK rising to LRCLK edge (see Note 5)
50
ns
Delay time, SDOUT valid from SCLK falling
100
ns
Setup time, SDIN before SCLK rising edge
10
ns
Hold time, SDIN from SCLK rising edge
100
ns
3.6
PARAMETER
MIN
MAX
UNIT
f(scl)
tBUF
tw(low)
tw(high)
th(STA)
tsu(STA)
th(DAT)
tsu(DAT)
tr
tf
tsu(STO)
A device must internally provide a hold time of at least 300 ns for the SDA signal to bridge the undefined region of the
falling edge of SCL.
NOTES:
6. tw(low) is measured from the end of tf to the beginning of tr.
7. tw(high) is measured from the end of tr to the beginning of tf.
SCL clock frequency
0
100
kHz
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
ns
Bus free time between start and stop
4.7
Pulse duration, SCL clock low (see Note 6)
4.7
Pulse duration, SCL clock high (see Note 7)
4
Hold time, repeated start
4
Setup time, repeated start
4.7
0
20
Hold time, data
Setup time, data
250
Rise time for SDA and SCL
1000
ns
Fall time for SDA and SCL
300
ns
μ
s
Setup time for stop condition
4
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD81CDBT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
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| TLC320AD91 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio Codec |
| TLC320AD91CPT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TLC320V320CFN | 制造商:Texas Instruments 功能描述: |
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