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參數(shù)資料
| 型號： | TLC320AD81C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Stereo Audio Digital Equalizer DC |
| 中文描述： | 立體聲音頻數(shù)字均衡器直流 |
| 文件頁數(shù)： | 21/47頁 |
| 文件大?。?/td> | 185K |
| 代理商： | TLC320AD81C |
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2–9
2.11 Device Initialization
2.11.1
Reset
The reset pin allows the device to be reset. That is the TLC320AD81C returns to its default state as defined
in this section. The device does not reset automatically when power is applied to the device. A reset is
required after the following condition occurs:
1.
Power is applied to any of the power pins.
Or before the following conditions occur:
1.
The main control register is written to.
2.
Any biquad register is written to.
2.11.2
Device Power On Plus Reset
When power is applied to the TLC320AD81C, the device will power up in an unknown state. It must be reset
before the device will be in a known state. Upon reset, the EQDAC will initialize to its default state (fast load
mode). The main control register will be configured to 1XXXXXXX, where X is don’t care, as shown in
Figure 2–7. Only the fast load bit will be set to a 1 in the main control register. This puts the device into fast
load mode (see section 2.12.1, Fast Load). All random access memory (RAM) will be initialized (previous
data will be overwritten).
Bit 7
Bit 0
1
X
X
X
X
X
X
X
Figure 2–6. Main Control Register
The I
2
C address pins (CS1 and CS2) should be driven or biased to set the TLC320AD81C to a known I
2
C
address. This also ensures the I
2
C port will be active immediately after the reset initialization phase.
Furthermore, when implementing a three or six speaker system, the CS1 and CS2 pins must always be
driven or set to unique addresses on all devices. If the DM pin is not driven, the internal bias will pull the pin
to a high logic level and de-emphasis will be on. If the SMUTE pin is not driven, the internal bias will pull the
pin to a low logic level and mute will be off. DM is not valid for any sampling frequency except 44.1 kHz. MCLK
must be driven by a 256 f
s
clock. The I
2
C port will be powered up but will not acknowledge any I
2
C bus activity
until the entire device has been initialized. This typically takes 5 ms for the TLC320AD81C to fully initialize
from a powered off state or all power supply pins = 0 V.
2.11.3
Fast Load
Upon entering fast load mode, the following occurs in addition to initialization:
1.
2.
3.
4.
All of the parametric EQ will be initialized to 0 dB (all-pass).
The tone (bass/treble) will be set to 0 dB.
The mix function will set SDIN1 to 0 dB and SDIN2 to mute (no-pass).
The volume will be set to mute.
While in fast load mode, it is possible to update the parametric EQ without any audio processing delay. The
audio processor will be paused while the RAM is being updated in this mode. It is recommended that
parametric EQ be downloaded in this mode. Bass and treble may not be downloaded in this mode. Mixer1
and Mixer2 registers may be downloaded in this mode or normal mode (FL bit = 0). It is not recommended
to download the volume control register and mixer registers in this mode. Once the download is complete,
the fast load bit needs to be cleared by writing a 0 into bit 7 of the main control register. This puts the
TLC320AD81C into normal mode.
NOTE:
When writing to the FL bit in the MCR, the audio serial format is also written to at
this time. However, the device will not recognize any serial audio until it has
returned to normal mode. Entering fast load mode only by resetting the
TLC320AD81C is recommended. Once back in normal mode, treble, bass, and
volume control may be downloaded to complete device setup.
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相關(guān)代理商/技術(shù)參數(shù) |
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| TLC320AD81CDBT | 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
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| TLC320AD91 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Stereo Audio Codec |
| TLC320AD91CPT | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TLC320V320CFN | 制造商:Texas Instruments 功能描述: |
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