參數(shù)資料
型號: TLC320AD81C
廠商: Texas Instruments, Inc.
英文描述: Stereo Audio Digital Equalizer DC
中文描述: 立體聲音頻數(shù)字均衡器直流
文件頁數(shù): 16/47頁
文件大?。?/td> 185K
代理商: TLC320AD81C
2–4
2.7
Right-Justified Serial Format
MSB
X
SDIN1
SCLK
MSB
X
LSB
LSB
MSB
X
MSB
X
LSB
LSB
Left Channel
Right Channel
SDOUT
LRCLK = fs
Figure 2–3. Right-Justified Serial Format
2.7.1
Protocol
LRCLK = Sampling frequency (f
s
)
Left channel is transmitted when LRCLK is high
1.
2.
3.
The SDIN1 data is justified to the trailing edge of the LRCLK
4.
Serial data is sampled on the rising edge of SCLK
5.
Serial data is transmitted on the falling edge of SCLK
6.
7.
SCLK = 64 LRCLK
In this mode, LRCLK does not have to be a 50% duty cycle clock. The number of bits used in the
interface sets the minimum duty cycle. There must be enough SCLK pulses to shift all of the data.
2.7.2
Implementation
LRCLK and SCLK are both inputs
1.
2.7.3
See Figure 4–1 for I
2
S timing.
Timing
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