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參數(shù)資料
| 型號(hào)： | TLC320AD75C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 20-Bit Sigma-Delta Stereo ADA Circuit |
| 中文描述： | 20位Σ-Δ立體聲電路反傾銷協(xié)定 |
| 文件頁(yè)數(shù)： | 23/43頁(yè) |
| 文件大?。?/td> | 211K |
| 代理商： | TLC320AD75C |
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2–11
Table 2–4. System Mode Register
D16
D15
D14
D13
D12–D5
D4
D3
D2
D1
DESCRIPTION
0
-
-
-
-
-
-
-
-
Reserved
-
0
-
-
-
-
-
-
-
Resynchronize
Off
-
1
-
-
-
-
-
-
-
On
-
-
0
0
-
-
-
-
-
44.1 kHz
-
-
0
1
-
-
-
-
-
Sample rate/
de emphasis
de-emphasis
selection
Reserved
-
-
1
0
-
-
-
-
-
48 kHz
-
-
1
1
-
-
-
-
-
32 kHz
-
-
-
-
0
-
-
-
-
Reserved
-
-
-
-
-
0
-
-
-
Input data word width
Input-data word width
20 bits audio data
-
-
-
-
-
1
-
-
-
16 bits audio data
-
-
-
-
-
-
0
-
-
Input D data protocol
Input D-data protocol
MSB first
-
-
-
-
-
-
1
-
-
LSB first
-
-
-
-
-
-
-
0
-
DAC register select
Attenuator-mode
register
-
-
-
-
-
-
-
-
-
-
-
-
1
-
-
0
System-mode register
Normal
-
DAC mode
-
-
-
-
-
-
-
-
1
Factory test only
The initialization value is 0000h.
2.19 Auto-Resynchronization Functionality
The TLC320AD75C has an auto-resynchronization function to keep the entire coversion cycle for the ADC
portion and DAC portion respectively checking the LRCK cycle of the f
s
rate. When the ADC is in slave mode,
the ADC portion has a window of
4 clocks of the internal 64 f
s
clock to check the LRCK cycle with the f
s
rate detecting the rising edge of LRCK within this window. When an error is detected on the LRCK cycle,
the ADC conversion cycle is resynchronized with an external LRCK cycle at the next rising edge of LRCK.
This resynchronization occurrs automatically and the ADC portion continues processing based on the new
conversion cycle timing.
The DAC portion has a window of
the rising edge of the LRCK clock. When an error is detected, the conversion cycle of the DAC is
resynchronized with an external LRCK cycle automatically and the DAC portion continues processing based
on the new conversion cycle timing. (The external LRCK rate should be the same as the fs rate. This
functionality is to ensure the TLC320AD75C conversion operation even if LRCK has a timing problem due
to noise injection for example.)
2 clocks of the internal 128 f
s
clock to check the LRCK cycle detecting
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC320AD77C | 24-BIT 96 kHz STEREO AUDIO CODEC |
| TLC320AD80C | Audio Processor Subsystem |
| TLC320AD81CDBT | Stereo Audio Digital Equalizer DC |
| TLC320AD81C | Stereo Audio Digital Equalizer DC |
| TLC339CDB | LinCMOSE MICROPOWER QUAD COMPARATORS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD75CDL | 制造商:Texas Instruments 功能描述: |
| TLC320AD77 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit 96 kHz Stereo Audio Codec |
| TLC320AD77C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-BIT 96 kHz STEREO AUDIO CODEC |
| TLC320AD77CDB | 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLC320AD77CDBG4 | 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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