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參數(shù)資料
| 型號： | TLC320AD75C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 20-Bit Sigma-Delta Stereo ADA Circuit |
| 中文描述： | 20位Σ-Δ立體聲電路反傾銷協(xié)定 |
| 文件頁數(shù)： | 19/43頁 |
| 文件大小： | 211K |
| 代理商： | TLC320AD75C |
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2–7
2.11 Serial-Control Interface for DAC
The TLC320AD75C uses the most-significant-bit-first format. Therefore, for a 16-bit data word, D16 is the
most significant bit (MSB) and D1 is the least significant bit (LSB).
2.11.1
The 16-bit control-data input implements the device-control functions. The TLC320AD75C has two registers
for this data: the system register and the attenuation register. The system register contains most of the
system configuration information, and the attenuation register controls the audio output level and
deemphasis. Figure 2–7 illustrates the input timing for CDIN, SHIFT, and LATCH. The data loads internally
during the low level of LATCH. The shift clock must be high or low for the LATCH setup time before LATCH
goes low.
Serial-Control-Data Input
As shown in Figure 2–7, CDIN is a 24-bit data stream consisting of 16 bits of control data D16 through D1
followed by 8 bits of device, address A8 through A1. When the TLC320AD75C receives address >E7h, the
control data is latched into the device by LATCH. For all other addresses, the data is ignored.
D16 D15
D14
D13
D12
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
A8
A7
A6
A5
A4
A3
A2
A1
Control Data
Control-Device Address
CDIN
SHIFT
LATCH
Figure 2–7. Control-Data Input Timing
2.12 DAC De-emphasis Filter
Three sets of de-emphasis-filter coefficients support the three sampling rates (f
s
): 32 kHz, 44.1 kHz, and
48 kHz. Internal system-register values select the filter coefficients. The internal register values enable or
disable the filter. Figure 2–8 illustrates the de-emphasis filtering characteristics.
Many audio sources have been recorded with pre-emphasis characteristics that are the inverse of the
characteristics shown in Figure 2–8. This device provides reconstruction of the original frequency response.
0
10
–10
R
De-emphasis
3.18
(50
μ
s)
10.6
(15
μ
s)
f – Frequency – kHz
Figure 2–8. De-emphasis Filter Characteristics
2.13 Digital Filter Mute for DAC
When the mute bit in the attenuation register is set to 1, the DAC digital filter mute is active. The output of
the digital filter is 0 + dc offset. Operation of the digital filter is normal during mute.
相關PDF資料 |
PDF描述 |
|---|---|
| TLC320AD77C | 24-BIT 96 kHz STEREO AUDIO CODEC |
| TLC320AD80C | Audio Processor Subsystem |
| TLC320AD81CDBT | Stereo Audio Digital Equalizer DC |
| TLC320AD81C | Stereo Audio Digital Equalizer DC |
| TLC339CDB | LinCMOSE MICROPOWER QUAD COMPARATORS |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD75CDL | 制造商:Texas Instruments 功能描述: |
| TLC320AD77 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-Bit 96 kHz Stereo Audio Codec |
| TLC320AD77C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:24-BIT 96 kHz STEREO AUDIO CODEC |
| TLC320AD77CDB | 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
| TLC320AD77CDBG4 | 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類型: 分辨率: 轉換速率:48 kSPs 接口類型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel |
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