參數(shù)資料
型號(hào): TLC320AD75C
廠商: Texas Instruments, Inc.
英文描述: 20-Bit Sigma-Delta Stereo ADA Circuit
中文描述: 20位Σ-Δ立體聲電路反傾銷(xiāo)協(xié)定
文件頁(yè)數(shù): 14/43頁(yè)
文件大?。?/td> 211K
代理商: TLC320AD75C
2–2
During general operation of the ADC, APD is recommended to be pulled high (APD is not needed for a reset).
When using the analog power-down mode (APD low), the following timing procedure is required to start all
of the ADC since the analog modulator portion which includes the external portion needs to be settled after
APD is high.
APD
> 100 msec
> 26 fs
DPD
LRCKA
ADOUT
Figure 2–1. ADC Start-Up Timing
2.1.3
When INIT is brought low, an internal reset signal becomes active approximately 120 cycles of the sampling
frequency (f
s
) after the falling edge of INIT. Under this condition, all internal circuits are initialized and the
PWM output is held at zero data (50% duty cycle). When INIT is brought high, the internal reset signal goes
inactive for a maximum of five LRCKD periods after the rising edge of INIT. At this point, internal clocks are
synchronous with LRCKD and the PWM output is valid (see Figure 2–2). LRCKD must be applied for proper
initialization.
Reset/Initialization for DAC
120 Cycles of fs
5 periods max
INIT
Internal
Reset
LRCKD
Figure 2–2. DAC-Reset Timing Relationships
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TLC320AD75CDL 制造商:Texas Instruments 功能描述:
TLC320AD77 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:24-Bit 96 kHz Stereo Audio Codec
TLC320AD77C 制造商:TI 制造商全稱(chēng):Texas Instruments 功能描述:24-BIT 96 kHz STEREO AUDIO CODEC
TLC320AD77CDB 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel
TLC320AD77CDBG4 功能描述:接口—CODEC STEREO AUDIO ADA RoHS:否 制造商:Texas Instruments 類(lèi)型: 分辨率: 轉(zhuǎn)換速率:48 kSPs 接口類(lèi)型:I2C ADC 數(shù)量:2 DAC 數(shù)量:4 工作電源電壓:1.8 V, 2.1 V, 2.3 V to 5.5 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:DSBGA-81 封裝:Reel