- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384004 > TLC320AD57C (Texas Instruments, Inc.) Sigma-Delta Stereo Analog-to-Digital Converter PDF資料下載
參數(shù)資料
| 型號(hào)： | TLC320AD57C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Sigma-Delta Stereo Analog-to-Digital Converter |
| 中文描述： | Σ-Δ立體聲模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 9/21頁 |
| 文件大?。?/td> | 133K |
| 代理商： | TLC320AD57C |
2–1
2 Detailed Description
The following sections contain a detailed description of the TLC320AD57C.
2.1
The following sections contain descriptions of the power-down and reset functions of the TLC320AD57C.
Power-Down and Reset Functions
2.1.1
The power-down state is comprised of a separate digital and analog power down. The power consumption
of each is detailed in Section 3.3, Electrical Characteristics.
Power Down
The digital power-down mode shuts down the digital filters and clock generators. All digital outputs are set
to an unasserted level. When the digital power-down terminal (DigPD) is pulled low, normal operation of the
device is initiated.
In slave mode, the conversion process must synchronize to an input on the LRClk terminal and the SCLK
terminal. Therefore, the conversion process is not initiated until the first rising edges on both SCLK and
LRClk are detected after DigPD is pulled low. This synchronizes the conversion cycle. All conversions are
performed at a fixed LRClk rate [MCLK/256 (CMODE low) or MCLK/384 (CMODE high)] after the initial
synchronization. After the digital power-down terminal is brought low, the output of the digital filters remains
invalid for 50 LRClk cycles [see Figures 2–1(a) and 2–1(b)].
In master mode, LRClk is an output; therefore, the conversion process initiates based on internal timing.
The first valid data out occurs as shown in Figure 2–1(c).
The analog power-down mode disables the analog modulators. The single-bit modulator outputs become
invalid, which renders the outputs of the digital filters invalid. When the analog power-down terminal is
brought low, the modulators are brought back online; however, the outputs of the digital filters require 50
LRClk cycles for valid results.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TLC320AD58(中文) | Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC) |
| TLC320AD58C | Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD75C | 20-Bit Sigma-Delta Stereo ADA Circuit |
| TLC320AD77C | 24-BIT 96 kHz STEREO AUDIO CODEC |
| TLC320AD80C | Audio Processor Subsystem |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD57CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD57CDWR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD58 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD58C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD58CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。