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參數(shù)資料
| 型號： | TLC320AD57C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Sigma-Delta Stereo Analog-to-Digital Converter |
| 中文描述： | Σ-Δ立體聲模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁數(shù)： | 15/21頁 |
| 文件大?。?/td> | 133K |
| 代理商： | TLC320AD57C |
3–1
3 Specifications
3.1
Absolute Maximum Ratings Over Operating Free-Air Temperature Range
(Unless Otherwise Noted)
Analog supply voltage range, AV
DD
(see Note 1)
Digital supply voltage range, DV
DD
(see Note 2)
Digital output voltage range, (externally applied)
Digital input voltage range, MODE0 – MODE2
Analog input voltage range, INLP, INLM, INRP, INRM
Operating free-air temperature range, T
A
Storage temperature range, T
stg
Case temperature for 10 seconds, T
C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
–0.3 V to 6.5 V
–0.3 V to 6.5 V
. . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . .
. . . . . . . . . . .
. . . . . . . . . . . .
. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.3 V to DV
DD
–0.3 V to DV
DD
–0.3 V to AV
DD
0.3 V
0.3 V
0.3 V
0
°
C to 70
°
C
–65
°
C to 150
°
C
260
°
C
260
°
C
. . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.
NOTES:
1. Voltage values for maximum ratings are with respect to AVSS.
2. Voltage values for maximum ratings are with respect to DVSS.
3.2
Recommended Operating Conditions
MIN
NOM
MAX
UNIT
Analog supply voltage, AVDD (see Note 3)
Digital supply voltage, DVDD
Analog logic supply voltage, at Vlogic
4.75
5
5.25
V
4.75
5
5.25
V
4.75
5
5.25
V
Reference voltage, Vref
Setup time, DigPD
↓
to LRClk
↑
, slave mode, tsu1 (see Figure 2–1(a))
Setup time, DigPD
↓
to LRClk
↑
, master mode, tsu2 (see Figure 2–1(b))
Setup time, SCLK
↑
to LRClk, slave mode, tsu3 (see Figures 4–5 and 4–6)
Setup time, LRClk to SCLK
↑
, slave mode, tsu4 (see Figure 4–5)
Setup time, SCLK
↑
to Fsync, slave mode, tsu5 (see Figure 4–6)
Setup time, Fsync to SCLK
↑
, slave mode, tsu6 (see Figure 4–6)
Load resistance at DOUT, RL
Operating free-air temperature, TA
NOTE 3: Voltages at analog inputs and outputs and AVDD are with respect to the AVSS terminal.
3.2
V
30
ns
30
ns
30
ns
30
ns
30
ns
30
ns
k
°
C
10
0
70
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