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參數(shù)資料
| 型號(hào)： | TLC320AD57C |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | Sigma-Delta Stereo Analog-to-Digital Converter |
| 中文描述： | Σ-Δ立體聲模擬數(shù)字轉(zhuǎn)換器 |
| 文件頁(yè)數(shù)： | 14/21頁(yè) |
| 文件大?。?/td> | 133K |
| 代理商： | TLC320AD57C |
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2–6
2.8.2
As a slave, the TLC320AD57C receives LRClk, Fsync, and SCLK as inputs. The conversion cycle
synchronizes to the rising edge of LRClk, and the data synchronizes to the falling edge of SCLK. SCLK must
meet the setup time requirements specified in Section 3.2, Recommended Operating Conditions.
Synchronization of the slave modes is accomplished with the digital power-down control.
Slave Mode
In slave mode, Fsync is an input. Three modes are provided as shown in Figures 2–4(a) through 2–4(c).
SCLK and LRClk are externally generated and sourced. The first rising edges of SCLK and LRClk after a
power-down cycle initiate the conversion cycle. Refer to Section 2.8.1, Master Mode for signal functions.
Several modes are available when the TLC320AD57C is configured as a slave. Using the Mode0, Mode1,
and Mode2 terminals, the TLC320AD57C can be set to shift out the MSB first or the LSB first [see Figures
2–4(a) and 2–4(b)]. The number of bits shifted out can be controlled by the number of valid SCLK cycles
provided within the left or right channel period. If only enough clocks are provided to shift out 16 data bits
before LRClk changes state, this is equivalent to a 16-bit mode.
. . .
17
16
. . .
1
0
17
16
. . .
1
0
SCLK
Fsync
DOUT
input
LRClk
Mode 000
(a) SLAVE MODE (Fsync high)
(b) SLAVE MODE (Fsync high)
SCLK
Fsync
DOUT
LRClk
Mode 001
input
output
input
0
1
. . .
16
17
0
1
. . .
16
17
64 SCLKs
17
. . .
0
17
. . .
0
17
. . .
0
17
0
32–128 SCLKs
(c) SLAVE MODE (Fsync controlled)
SCLK
Fsync(1)
DOUT(1)
Mode 010
LRClk
Fsync(2)
DOUT(2)
Left
Left
Right
Left
32–128 SCLKs
Right
Right
Figure 2–4. Serial Slave Transfer Modes
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| TLC320AD58(中文) | Sigma-Delta Analog Interface Circuit(Sigma-Delta立體聲音頻ADC) |
| TLC320AD58C | Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD75C | 20-Bit Sigma-Delta Stereo ADA Circuit |
| TLC320AD77C | 24-BIT 96 kHz STEREO AUDIO CODEC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TLC320AD57CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD57CDWR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD58 | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD58C | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
| TLC320AD58CDW | 制造商:TI 制造商全稱:Texas Instruments 功能描述:Sigma-Delta Stereo Analog-to-Digital Converter |
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