
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
VCO1, VCO2 operating characteristics, V
DD
= 3 V, T
A
= 25
°
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
RBIAS1, RBIAS2 = 3.3 k
,
VCOIN1, VCOIN2 = 1/2 VDD
See Note 8
MIN
TYP
MAX
UNIT
fosc
Operating oscillation frequency
15
19
23
MHz
ts(fosc)
Time to stable oscillation
10
μ
s
tr
Rise time
CL = 15 pF,
CL = 50 pF,
CL = 15 pF,
CL = 50 pF,
RBIAS1, RBIAS2 = 3.3 k
,
VCOIN1, VCOIN2 = 1/2 VDD
RBIAS1, RBIAS2 = 3.3 k
,
VCOIN1, VCOIN2 = 1/2 VDD,
TA = –20
°
C to 75
°
C
RBIAS1, RBIAS2 = 3.3 k
,
VCOIN1, VCOIN2 = 1.5 V,
VDD = 2.85 V to 3.15 V
RBIAS1 = 3.3 k
See Figure 3
7
14
ns
See Figure 3
14
tf
Fall time
See Figure 3
6
12
ns
See Figure 3
10
Duty cycle at VCO OUT
45%
50%
55%
α(
fosc)
Temperature coefficient of oscillation frequency
0.04
%/
°
C
kSVS(fosc)
Supply voltage coefficient of oscillation frequency
0.02
%/mV
Jitter absolute (see Note 9)
100
ps
NOTES:
8. The time period to stabilize the VCO oscillation frequency after VCOINHIBIT is changed to a low level.
9. The LPF circuit is shown in Figure 28 with calculated values listed in Table 9. Jitter performance is highly dependent on circuit layout
and external device characteristics. The jitter specification was made with a carefully designed PCB with no device socket.
PFD1, PFD2 operating characteristics, V
DD
= 3 V, T
A
= 25
°
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
fmax
tPLZ
tPHZ
tPZL
tPZH
tr
tf
Maximum operating frequency
20
MHz
PFD output disable time from low level
21
50
ns
PFD output disable time from high level
See Figures 4 and 5 and Table 4
23
50
PFD output enable time to low level
11
30
ns
PFD output enable time to high level
10
30
Rise time
Fall time
CL= 15 pF
CL = 15 pF,
See Figure 4
2.3
2.1
10
10
ns
ns