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參數(shù)資料
| 型號： | TLC2942PW |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK |
| 中文描述： | 高效能雙鎖相環(huán)積木 |
| 文件頁數(shù)： | 22/28頁 |
| 文件大?。?/td> | 459K |
| 代理商： | TLC2942PW |
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TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
APPLICATION INFORMATION
basic design example
The following design example presupposes that the input reference frequency and the required frequency of
the VCO are within the respective ranges of the device.
Assume the loop has to have a 100-
μ
s settling time (t
s
) with a countdown divider N value = 8. Using the Type
1, second-order response curves of Figure 26, a value of 4.5 radians is selected for
ω
n
t
s
with a damping factor
of 0.7. This selection gives a good combination for settling time, accuracy, and loop gain margin. The initial
parameters are summarized in Table 7. The loop constants, K
V
and K
p
, are calculated from the data sheet
specifications and Table 8 shows these values.
The natural loop frequency is calculated as follows:
nts
4.5
Then
n
4.5
100
s
45 k-radians sec
Since
(4)
Table 7. Design Parameters
PARAMETER
SYMBOL
VALUE
UNITS
Divider value
N
8
Lockup time
t
100
μ
s
rad
Radian value to selected lockup time
ω
nt
ζ
4.5
Damping factor
0.7
Table 8. Device Specifications
PARAMETER
SYMBOL
VALUE
UNITS
VCO gain
76.6
Mrad/V/s
fMAX
fMIN
VIN MAX
VIN MIN
PFD gain
70
MHz
KV
20
MHz
5
V
0.9
V
Kp
0.342357
V/rad
Using the low-pass filter in Figure 25(b) and divider N value, the transfer function for phase and frequency are
shown in equations 5 and 6. Note that the transfer function for phase differs from the transfer function for
frequency by only the divider N value. The difference arises from the fact that the feedback for phase is unity
while the feedback for frequency is 1/N.
Hence, transfer function of Figure 24 (a) for phase is:
2(s)
1(s)
Kp
KV
N
(T1
T2)
1
s
T2
T2
T2)
s2
s
1
KpKV
N (T1
KpKV
N (T1
T2)
(5)
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