參數(shù)資料
型號(hào)： TLC2942PW
廠商： Texas Instruments, Inc.
英文描述： HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
中文描述： 高效能雙鎖相環(huán)積木
文件頁(yè)數(shù)： 10/28頁(yè)
文件大小： 459K
代理商： TLC2942PW
TLC2942
HIGH-PERFORMANCE DUAL PHASE-LOCKED LOOP BUILDING BLOCK
SLAS146B – NOVEMBER 1996 – REVISED JUNE 1997
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
VCO1, VCO2 electrical characteristics, V
DD
= 5 V, T
A
= 25
°
C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
VIT
High-level output voltage
IOH = –2 mA
IOL = 2 mA
4
V
Low-level output voltage
0.5
V
Input threshold voltage
SELECT1, SELECT2,
VCOINHIBIT1, VCOINHIBIT2
1.5
2.5
3.5
V
II
Input current
SELECT1, SELECT2,
VCOINHIBIT1, VCOINHIBIT2
VI = VDD or GND
±
1
μ
A
Zi(VCOIN)
IDD(INH)
IDD(VCO)
NOTES: 4. The current into VCO VDD and LOGIC VDD when VCOINHIBIT = VDD, and the PFD is inhibited.
10. The current into VCO VDD and LOGIC VDD when VCOIN = 1/2 VDD, RBIAS = 2.2 k
, VCOINHIBIT = GND, and the PFD is inhibited.
PFD1, PFD2 electrical characteristics, V
DD
= 5 V, T
A
= 25
°
C (unless otherwise noted)
PARAMETER
Input impedance
VCOIN1, VCOIN2
VCOIN = 1/2 VDD
See Note 4
10
M
μ
A
mA
VCO supply current (inhibit) (each chip)
0.01
1
VCO supply current (each chip)
See Note 10
15
35
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VOH
VOL
High-level output voltage
IOH = 2 mA
IOL = 2 mA
PFD INHIBIT1, PFD INHIBIT2 = high,
VO = VDD or GND
4.5
V
Low-level output voltage
0.2
V
IOZ
High-impedance output current
±
1
μ
A
VIH
High-level input voltage
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
PFD INHIBIT2,
PFD INHIBIT1
4.5
V
VIL
Low-level input voltage
1
V
VIT
Input threshold voltage
1.5
2.5
3.5
V
Ci
Input capacitance
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
FIN–A1, FIN–B1,
FIN–A2, FIN–B2
5
pF
Zi
Input impedance
10
M
IDD(Z)
IDD(PFD)
NOTES:
High-impedance state PFD supply current
See Note 6
0.1
1
μ
A
mA
PFD supply current (each chip)
See Note 11
0.15
3
6. The current into LOGIC VDD, when FIN–A and FIN–B = GND, PFD INHIBIT= VDD, no load, and VCO OUT is inhibited.
11. The current into LOGIC VDD when FIN–A and FIN–B = 1 MHz with VI(PP) = 5-V rectangular wave, PFD INHIBIT = GND, no load,
and
VCO OUT is inhibited.
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