參數資料
型號: TG80960JA-25
廠商: INTEL CORP
元件分類: 微控制器/微處理器
英文描述: EMBEDDED 32-BIT MICROPROCESSOR
中文描述: 32-BIT, 25 MHz, RISC PROCESSOR, PQFP132
封裝: PLASTIC, QFP-132
文件頁數: 9/78頁
文件大?。?/td> 835K
代理商: TG80960JA-25
Advance Information Datasheet
9
80960JA/JF/JD/JT 3.3 V Microprocessor
2.1
80960 Processor Core
The 80960Jx family is a scalar implementation of the 80960 Core Architecture. Intel designed this
processor core as a very high performance device that is also cost-effective. Factors that contribute
to the core’s performance include:
Core operates at the bus speed with the 80960JA/JF
Core operates at two or three times the bus speed with the 80960JD and 80960JT respectively
Single-clock execution of most instructions
Independent Multiply/Divide Unit
Efficient instruction pipeline minimizes pipeline break latency
Register and resource scoreboarding allow overlapped instruction execution
128-bit register bus speeds local register caching
Two-way set associative, integrated instruction cache
Direct-mapped, integrated data cache
1 Kbyte integrated data RAM delivers zero wait state program data
Figure 2.
80960Jx Block Diagram
Programmable
Interrupt Controller
Control
Address/
Data Bus
Instruction Sequencer
Physical Region
Configuration
Interrupt
Port
1K Data RAM
Memory
Interface
Unit
Execution
and
Multiply
Divide
Unit
Memory-Mapped
Register Interface
Global / Local
Register File
SRC2 DEST
SRC1
Control
address
Constants
Generation
Unit
Address
32-bit Address
32-bit Data
Bus Request
Queues
Two 32-Bit
Timers
8-Set
Local Register Cache
S
S
D
PLL, Clocks,
Power Mgmt
Boundary Scan
Controller
TAP
5
CLKIN
S
S
D
S
D
9
32
32-bit buses
address / data
21
Instruction Cache
80960JA - 2K
80960JF/JD - 4K
80960JT - 16K
Two-Way Set Associative
Direct Mapped
Data Cache
80960JA - 1K
80960JF/JD - 2K
80960JT - 4K
128
3 Independent 32-Bit SRC1, SRC2, and DEST Buses
CoBus
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