參數(shù)資料
型號(hào): TFP503PZP
廠商: Texas Instruments, Inc.
英文描述: PANELBUS HDCP DIGITAL RECEIVER
中文描述: PANELBUS支持HDCP數(shù)字接收機(jī)
文件頁(yè)數(shù): 9/27頁(yè)
文件大?。?/td> 445K
代理商: TFP503PZP
SLDS149 AUGUST 2004
9
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
ac specifications (continued)
PARAMETER
TEST CONDITIONS
ST = Low
CL = 10 pF
ST = High
CL = 10 pF
ST = Low
CL = 10 pF
ST = High
CL = 10 pF
ST = Low
CL = 10 pF
ST = High
CL = 10 pF
ST = Low
CL = 10 pF
ST = High
CL = 10 pF
ST = Low
CL = 10 pF
ST = High
CL = 10 pF
MIN
TYP
MAX
UNIT
1 pixel/clock
PIXS = Low
1.9
ns
OCK_INV = High
1.9
tsu(2)
Setup time, data, and control signals to
rising edge of ODCK (see Note 11)
2 pixel/clock
PIXS = High
2.9
ns
STAG = High
OCK_INV = High
2.9
2 pixel & STAG
PIXS = High
2.0
ns
STAG = Low
OCK_INV = High
2.0
1 pixel/clock
PIXS = Low
0.5
ns
th(2)
Hold time, data, and control signals to
rising edge of ODCK (see Note 11)
OCK_INV = High
0.5
2 pixel & STAG
PIXS = High
1.4
ns
STAG = Low
OCK_INV = High
1.4
f(ODCK)
ODCK frequency
PIXS = Low
25
165
MHz
PIXS = High
12.5
82.5
ODCK duty cycle
40%
50%
60%
td(PDL)
td(PDOL)
Delay from PD low to Hi-Z outputs
18
ns
Delay from PDO low to Hi-Z outputs
18
ns
t(HSC)
Time between DE transitions to SCDT low
(see Note 13)
165 MHz
25
ms
tt(FSC)
Time from DE low to SCDT high
(see Note 13)
8
trans(DE)
td(st)
ODCK latching edge to QE[23:0] data
output
trans(DE) is one transition (low-to-high or high-to-low) of the DE signal.
NOTES: 11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1].
13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
STAG = Low
PIXS = High
0.5
t(pixel)
ns
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