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參數(shù)資料
| 型號： | TFP503PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PANELBUS HDCP DIGITAL RECEIVER |
| 中文描述： | PANELBUS支持HDCP數(shù)字接收機 |
| 文件頁數(shù)： | 8/27頁 |
| 文件大小： | 445K |
| 代理商： | TFP503PZP |
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SLDS149 AUGUST 2004
8
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted) (continued)
ac specifications
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VID(2)
VID(3)
Differential input sensitivity (see Note 8)
150
mVpp
Maximum differential input
1560
mVpp
tsk(D)
Analog input intra-pair (+ to ) differential
skew (see Note 12)
0.4
t(bit)
1.0
t(pixel)
ns
tsk(CC)
Analog input inter-pair or channel-to-channel
skew (see Note 12)
ns
Worst case differential input clock jitter
tolerance (see Notes 9 and 12)
112 MHz, 1 pixel/clock
200
ps
tr(1)
Rise time of data and control signals
(see Notes 10 and 11)
ST = Low, CL = 10 pF
ST = High, CL = 10 pF
ST = Low, CL = 10 pF
ST = High, CL = 10 pF
ST = Low, CL = 10 pF
ST = High, CL = 10 pF
ST = Low, CL = 10 pF
ST = High, CL = 10 pF
1 pixel/clock
PIXS = Low
1.9
ns
1.9
tf(1)
Fall time of data and control signals
(see Notes 10 and 11)
1.9
ns
1.9
tr(2)
Rise time of ODCK clock (see Note 10)
1.9
ns
1.9
tf(2)
Fall time of ODCK clock (see Note 10)
1.9
ns
1.9
ST = Low
CL = 10 pF
ST = High
CL = 10 pF
ST = Low
CL = 10 pF
ST = High
CL = 10 pF
ST = Low
CL = 10 pF
ST = High
CL = 10 pF
ST = Low
CL = 10 pF
ST = High
CL = 10 pF
ST = Low
CL = 10 pF
ST = High
CL = 10 pF
1.2
ns
OCK_INV = Low
1.2
tsu(1)
Setup time, data, and control signals to falling
edge of ODCK (see Note 11)
2 pixel/clock
PIXS = High
2.7
ns
STAG = High
OCK_INV = Low
2.7
2 pixel & STAG
PIXS = High
1.7
ns
STAG = Low
OCK_INV = Low
1.7
1 pixel/clock
PIXS = Low
0.9
ns
th(1)
Hold time, data, and control signals to falling
edge of ODCK (see Note 11)
OCK_INV = Low
0.9
2 pixel and STAG
PIXS = High
2.9
ns
STAG = Low
OCK_INV = Low
2.9
t(bit) is 1/10 the pixel time, t(pixel)
t(pixel) is the pixel time defined as the period of the RxC input clock. The period of ODCK is equal to t(pixel) in 1-pixel/clock mode or 2 t(pixel) when
in 2-pixel/clock mode.
NOTES:
8. Specified as ac parameter to include sensitivity to overshoot, undershoot, and reflection.
9. Measured differentially at 50% crossing using ODCK output clock as trigger.
10. Rise and fall times measured as time between 20% and 80% of signal amplitude.
11. Data and control signals are: QE[23:0], QO[23:0], DE, HSYNC, VSYNC and CTL[2:1].
12. By characterization
13. Link active or inactive is determined by amount of time detected between DE transitions. SCDT indicates link activity.
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