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參數(shù)資料
| 型號： | TFP503PZP |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | PANELBUS HDCP DIGITAL RECEIVER |
| 中文描述： | PANELBUS支持HDCP數(shù)字接收機 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大小： | 445K |
| 代理商： | TFP503PZP |
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SLDS149 AUGUST 2004
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
TFP503 output driver configurations (continued)
Both PDO and PD have internal pullup resistors; so, if left unconnected, they default the TFP503 to normal
operating modes.
Sync detect.
The TFP503 offers an output, SCDT, to indicate link activity. The TFP503 monitors activity on DE
to determine if the link is active. When 1 million pixel clock periods pass without a transition on DE, the TFP503
considers the link inactive and SCDT is driven low. SCDT goes high immediately after the first eight transitions
on DE. SCDT again goes low when no more transitions are seen after 2
18
oscillator clocks.
SCDT can signal a system power-management circuit to initiate a system power down when the link is
considered inactive. The SCDT can also be tied directly to the TFP503 PDO input to power down the output
drivers when the link is inactive. It is not recommended to use the SCDT to drive the PD input since, once in
complete power down, the analog inputs are ignored and the SCDT state does not change. An external system
power management circuit to drive PD is preferred.
HDCP register map
The TFP503 is a standard I
2
C slave device. All the registers can be written and read through the I
2
C interface.
The I
2
C base address of the TFP503 is dependent on terminal 94 (DDC_SA) as shown below.
TERMINAL 94
WRITE ADDRESS (HEX)
READ ADDRESS (HEX)
0
74
75
1
76
77
I
2
C register map
BKSV
Subaddress = 00
Read Only
7
6
5
4
3
2
1
0
BKSV[7:0]
Subaddress = 01
Read Only
7
6
5
4
3
2
1
0
BKSV[15:8]
Subaddress = 02
Read Only
7
6
5
4
3
2
1
0
BKSV[23:16]
Subaddress = 03
Read Only
7
6
5
4
3
2
1
0
BKSV[31:24]
Subaddress = 04
Read Only
7
6
5
4
3
2
1
0
BKSV[39:32]
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