參數(shù)資料
型號： TFP503PZP
廠商： Texas Instruments, Inc.
英文描述： PANELBUS HDCP DIGITAL RECEIVER
中文描述： PANELBUS支持HDCP數(shù)字接收機(jī)
文件頁數(shù)： 4/27頁
文件大?。?/td> 445K
代理商： TFP503PZP
SLDS149 AUGUST 2004
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
AGND
NO.
79
Analog ground. Ground reference and current return for analog circuitry.
AVDD
82, 85,
88, 91
Analog VDD. Power supply for analog circuitry. Nominally 3.3 V.
CAP
67
O
Bypass capacitor. 4.7-
μ
F tantalum and 0.01-
μ
F ceramic capacitors connected to ground.
General-purpose control signals. Used for user-defined control. In normal mode, CTL1 is not powered down
via PDO.
Display data channel_serial address. I2C slave address bit A0 for display data channel (DDC). Refer to
I2C
interface
section for more details.
Display data channel_serial clock. I2C clock for the DDC. This terminal is 3.3-V tolerant and typically sinks
3 mA. External pullup resistors are required. A level translator must be used to interface to 5-V DDC lines.
Display data channel_serial data. I2C data for the DDC. This terminal is 3.3-V tolerant and typically sinks
3 mA. External pullup resistors are required. A level translator must be used to interface to 5-V DDC lines.
CTL[2:1]
41, 40
O
DDC_SA
94
I
DDC_SCL
92
I/O
DDC_SDA
93
I/O
DE
46
O
Output data enable. Indicates time of active video display versus nonactive display or blanking interval. During
blanking, only HSYNC, VSYNC, and CTL[2:1] are transmitted. During times of active display, or nonblanking,
only pixel data, QE[23:0] and QO[23:0], is transmitted.
High: active display interval
Low: blanking interval
DFO
1
I
Output clock data format. Controls the output clock (ODCK) format for either TFT or DSTN panel support. For
TFT support, the ODCK clock runs continuously. For DSTN support, the ODCK only clocks when DE is high;
otherwise, ODCK is held low when DE is low.
High: DSTN support/ODCK held low when DE is low.
Low: TFT support/ODCK runs continuously.
DGND
5, 39, 68
Digital ground. Ground reference and current return for digital core.
DVDD
HSYNC
6, 38
Digital VDD. Power supply for digital core. Nominally 3.3 V.
Horizontal sync output
48
O
OCK_INV
100
I
ODCK polarity. Selects the ODCK edge on which pixel data (QE[23:0] and QO[23:0]) and control signals
(HSYNC, VSYNC, DE, CTL[2:1]) are latched.
Normal mode:
High: latches output data on rising ODCK edge.
Low: latches output data on falling ODCK edge.
ODCK
44
O
Output data clock. Pixel clock. All pixel outputs QE[23:0] and QO[23:0] (if in 2-pixel/clock mode) along with
DE, HSYNC, VSYNC, and CTL[2:1] are synchronized to this clock.
OGND
19, 28,
45, 58,
76
Output driver ground. Ground reference and current return for digital output drivers.
OVDD
18, 29,
43, 57,
78
Output driver VDD. Power supply for output drivers. Nominally 3.3 V.
PD
2
I
Power down. An active low signal that controls the TFP503 power-down state. During power down, all output
buffers are switched to a high-impedance state and brought low through a weak pulldown resistor. All analog
circuits are powered down and all inputs are disabled, except for PD.
If PD is left unconnected, an internal pullup resistor defaults the TFP503 to normal operation.
High: normal operation
Low: power down
PDO
9
I
Output drive power down. An active low signal that controls the power-down state of the output drivers. During
output drive power down, the output drivers (except SCDT and CTL1) are driven to a high-impedance state. A
weak pulldown resistor slowly pulls these outputs to a low level. When PDO is left unconnected, an internal
pullup resistor defaults the TFP503 to normal operation.
High: normal operation/output drivers on
Low: output drive power down
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