參數(shù)資料
型號(hào)： TEA5766UK/N1/S21,0
廠商： NXP SEMICONDUCTORS
元件分類： 接收器
英文描述： FM, AUDIO SINGLE CHIP RECEIVER, PBGA25
封裝： 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25
文件頁(yè)數(shù)： 59/59頁(yè)
文件大小： 273K
代理商： TEA5766UK/N1/S21,0
TEA5766UK_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 22 March 2007
9 of 59
NXP Semiconductors
TEA5766UK
Stereo FM radio + RDS
test mode the software port outputs signals according to Table 21. Software test mode is
selected by setting bit TM of register TESTREG (see Table 19). The software port is not
disabled by the PUPD bits (see Section 7.16).
7.16 Standby mode
With the PUPD[1:0] (power-up/power-down) bits the radio can be put in Standby mode.
Standby mode is dened as where the TEA5766UK has all supply voltages available but
the circuits are powered down via software (PUPD) or after power-on reset. The RDS part
can be turned off separately, using one of the PUPD bits. After a power-on reset or when
the TEA5766UK is in Standby mode, the TEA5766UK is still accessible via the control
interface, but takes only a limited amount of power from the supply. The software
programmable port maintains active to allow peripheral devices to be controlled. The
audio outputs are hard-muted.
In I2C-bus mode when pin BUSEN = HIGH and the circuits are powered down via
software (PUPD) the TEA5766UK is in Sleep mode. In this Sleep mode the TEA5766UK
is accessible via the bus, but the radio part is not active. The IVREFDIG current is higher
than in Standby mode.
When the supply voltages VCCA and VCCD are made 0 V and pin VREFDIG = HIGH, all
I/Os, the audio outputs and the reference clock input are in high-impedance state. The
power supplies can be switched on in any order.
7.17 Power-on reset
After start-up of VCCA and VCCD, a power-on reset circuit will generate a reset pulse and
the registers will be set to their default values as shown in Table 12. The power-on reset is
effectively generated by VCCD. Power-on reset: the audio output pins are in
high-impedance state (hard mute) and all other bits are set default according to the tables
in Section 11. To initialize the TEA5766UK all bytes have to be transferred.
7.18 RDS/RBDS demodulator
Fully integrated RDS/RBDS demodulator, uses the reference frequency (32678 Hz) of the
PLL synthesizer tuning system. The RDS demodulator recovers and regenerates the
continuously transmitted RDS or RBDS data stream of the multiplex signal (MPXRDS)
and provides the signals clock (RDCL), data (RDDA) for further processing by the
integrated RDS decoder.
相關(guān)PDF資料
PDF描述
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TEA5767HN/V3 功能描述:射頻收發(fā)器 FM RECEIVER RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
TEA5767HN/V3,118 功能描述:射頻收發(fā)器 FM RECEIVER RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray
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