參數(shù)資料
型號(hào): TEA5766UK/N1/S21,0
廠(chǎng)商: NXP SEMICONDUCTORS
元件分類(lèi): 接收器
英文描述: FM, AUDIO SINGLE CHIP RECEIVER, PBGA25
封裝: 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25
文件頁(yè)數(shù): 17/59頁(yè)
文件大小: 273K
代理商: TEA5766UK/N1/S21,0
TEA5766UK_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 22 March 2007
24 of 59
NXP Semiconductors
TEA5766UK
Stereo FM radio + RDS
9.2 DAV-B processing mode and fast PI search mode
This mode is used when, for example, the receiver has been re-tuned to a new station and
a fast search of the PI code (always contained in the A/C’-block) is required. The diagram
shown in Figure 10, assumes that the RDS decoder is unsynchronized initially and is
performing a synchronization search.
During synchronization search the decoder does not set the DAVFLG until a valid
A/C’-block is detected. If a valid B-block is immediately detected, the decoder is
synchronized and the SYNC bit is set to logic 1. In fact, if any 2 good blocks in a valid
order are found the RDS decoder will synchronize and give an interrupt.
If for some reason a valid B block was not received the next valid A/C’-block is decoded
and the DAVFLG set. The BP and BL registers would record the A-block history.
After synchronization each decoded block will set the DAVFLG (assuming it was reset by
a read action) and generate an interrupt.
BBG = 3: synchronization is reached after receiving 1 good block and after 0, 1 or 2 bad blocks
and again a good block. After three bad blocks there will be no synchronization and the
counters will be reset waiting for a new good block.
Fig 10. DAV-B timing diagram
001aaf588
B1
21.9 ms
only valid blocks with no errors
are counted as good blocks
error correction applied
according to SYM bits
bad
good
bad
read BL register
read INTMSK
not synchronized
synchronized
DAVFLG
INTX
SYNC status bit
good A or C' block detected
bad
C'1
Bus access - read
D1
A2
B2
C2
BL register
x
BP register
C'1
B2
C2
xxx
x
C'1
B2
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