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| 型號： | TEA5766UK/N1/S21,0 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 接收器 |
| 英文描述： | FM, AUDIO SINGLE CHIP RECEIVER, PBGA25 |
| 封裝： | 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25 |
| 文件頁數(shù)： | 10/59頁 |
| 文件大?。?/td> | 273K |
| 代理商： | TEA5766UK/N1/S21,0 |
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TEA5766UK_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 22 March 2007
18 of 59
NXP Semiconductors
TEA5766UK
Stereo FM radio + RDS
8.2 Interrupt ags and behavior
8.2.1 Multiple interrupt events
If the interrupt mask register bit is set then the setting of an interrupt ag for that bit
causes a hardware interrupt (INTX goes LOW). If the event occurs again before the ag is
cleared, then this does not trigger any further hardware interrupts until that specic ag is
cleared. However two different events can occur in sequence and generate a sequence of
hardware interrupts. Only when read, followed by a write of the INTMSK byte has been
done, a second interrupt can be generated, as the rst interrupt blocks the input of the
INTX one-shot generator.
If subsequent interrupts occur within the INTX LOW period then these interrupts do not
cause the INTX period to extend beyond its specied maximum period. See also
8.2.2 Data available: DAVFLG
When a new block of data is received, the DAVFLG is set according to the diagrams
shown in Section 9 where the different DAV modes are described. Once synchronized,
this continues for all subsequent received blocks (dependent on DAV mode) and in the
following situations:
During synchronization search in any DAV mode, if two valid blocks in the correct
sequence are received with BBC < BBL (synchronized)
During synchronization search in DAV-B mode if a valid A(C’)-block has been
detected; this mode can be used for fast search tuning (detection and comparison of
the Program Identication (PI) code contained in the A(C’)-block)
If the pre-processor is synchronized and in mode DAV-A or DAV-B a new block has
been processed
If the pre-processor is synchronized and in DAV-C mode two new blocks have been
processed
If the decoder is synchronized and for any DAV mode, with LSYNCMSK = 0, loss of
synchronization is detected (ywheel loss of synchronization, resulting in a restart of
synchronization search)
The DAVFLG is reset by a read of BL[7:0] of RDSR2 (byte 15R) or BP[7:0] of RDSR3
(byte 17R). An interrupt is given each time when a new block of data is decoded and when
the DAVMSK is set; for details see Section 9.
8.2.3 RDS synchronization: LSYNCFL
The SYNC bit, (see Table 22) shows the status of the RDS decoder. If it is set the decoder
is synchronized.
The action of the TEA5766UK depends on the status of the LSYNCMSK bit in Table 8. If
this is set then the loss of synchronization causes the LSYNCFL to go logic 1 and a
hardware interrupt is generated. The RDS part of the TEA5766UK is set to idle and waits
for the host processor to initiate a new synchronization search by setting the NWSY bit as
described in Table 26.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| TEA5767 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:single-chip FM stereo radio |
| TEA5767HL | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-power FM stereo radio for handheld applications |
| TEA5767HN | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Low-power FM stereo radio for handheld applications |
| TEA5767HN/V3 | 功能描述:射頻收發(fā)器 FM RECEIVER RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
| TEA5767HN/V3,118 | 功能描述:射頻收發(fā)器 FM RECEIVER RoHS:否 制造商:Atmel 頻率范圍:2322 MHz to 2527 MHz 最大數(shù)據(jù)速率:2000 Kbps 調(diào)制格式:OQPSK 輸出功率:4 dBm 類型: 工作電源電壓:1.8 V to 3.6 V 最大工作溫度:+ 85 C 接口類型:SPI 封裝 / 箱體:QFN-32 封裝:Tray |
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