參數(shù)資料
型號: TEA5766UK/N1/S21,0
廠商: NXP SEMICONDUCTORS
元件分類: 接收器
英文描述: FM, AUDIO SINGLE CHIP RECEIVER, PBGA25
封裝: 3.30 X 3.25 MM, 0.60 MM HEIGHT, WLCSP-25
文件頁數(shù): 13/59頁
文件大?。?/td> 273K
代理商: TEA5766UK/N1/S21,0
TEA5766UK_1
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 01 — 22 March 2007
20 of 59
NXP Semiconductors
TEA5766UK
Stereo FM radio + RDS
After a search, a preset or an AF update the threshold for comparison is switched to the
hysteresis level. The hysteresis level is set by the combination of SSL bits and the LHSW
bit, which results in a hysteresis as shown in Table 20. Then the level ADC starts to run
automatically and compares the level each 500
s with the hysteresis level. The
LEVFLAG bit is set if the RSSI level drops below the threshold level set by the SSL bits in
combination with the LHSW bit. The hardware interrupt is only generated if the
corresponding mask bit is set. With the LHSW bit a small or a large hysteresis can be
selected, which results in the levels of the left RSSI hysteresis threshold column for
LHSW = 0 and in the right RSSI hysteresis threshold column (see Table 19).
Remark: when a search or preset is done with the ADC level set to 3 then when the
algorithm has nished, the threshold level is set to 0. Hence the LEVFLAG will never be
set.
The LEVFLAG bit is cleared by a read of the INTMSK byte 1R, or by starting the tuning
algorithm.
8.2.6 Frequency ready: FRRFLAG
The frequency ready ag bit is set when the automatic tuning has nished a search, a
preset or an RDS AF update. The function of this bit is described in Table 5 and Table 6.
The FRRFLAG is cleared by a read of byte 1R.
8.2.7 Band limit: BLFLAG
The band limit bit BLFLAG is set when the automatic tuning has detected the end of the
tuning band or when the PLL cannot lock on a certain frequency. The description of this bit
is in Table 5 and Table 6. This bit is cleared by a read of byte 1R.
8.3 Interrupt line: pin INTX
The interrupt line driver is a MOS transistor with a nominal sink current of 900
A, it is
pulled HIGH by an 18 k
resistor connected to pin VREFDIG. The interrupt line can be
connected to another similar device with an interrupt output and an 18 k
pull-up resistor,
providing a wired-OR function. This allows any of the drivers to pull the line LOW by
sinking the current as specied in Section 13.4. So when a ag is set and not masked it
generates an interrupt.
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