參數(shù)資料
型號(hào)： TE28F008S3-150
廠(chǎng)商： INTEL CORP
元件分類(lèi)： DRAM
英文描述： BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY 4, 8, AND 16 MBIT
中文描述： 1M X 8 FLASH 2.7V PROM, 150 ns, PDSO40
封裝： 10 X 20 MM, TSOP-40
文件頁(yè)數(shù)： 15/41頁(yè)
文件大?。?/td> 703K
代理商： TE28F008S3-150
E
BYTE-WIDE SMART 3 FlashFile MEMORY FAMILY
15
PRELIMINARY
Table 3. Command Definitions
(9)
Bus Cycles
First Bus Cycle
Second Bus Cycle
Command
Req’d.
Notes
Oper
(1)
Addr
(2)
Data
(3)
Oper
(1)
Addr
(2)
Data
(3)
Read Array/Reset
1
Write
X
FFH
Read Identifier Codes
≥
2
2
4
Write
X
90H
Read
IA
ID
Read Status Register
Write
X
70H
Read
X
SRD
Clear Status Register
1
Write
X
50H
Block Erase
2
5
Write
BA
20H
Write
BA
D0H
Program
2
5,6
Write
PA
40H
or
10H
Write
PA
PD
Block Erase and Program
Suspend
1
5
Write
X
B0H
Block Erase and Program
Resume
1
5
Write
X
D0H
Set Block Lock-Bit
2
7
Write
BA
60H
Write
BA
01H
Set Master Lock-Bit
2
7
Write
X
60H
Write
X
F1H
Clear Block Lock-Bits
2
8
Write
X
60H
Write
X
D0H
NOTES:
1. Bus operations are defined in Table 2.
2. X = Any valid address within the device.
IA = Identifier Code Address: see Figure 6.
BA = Address within the block being erased or locked.
PA = Address of memory location to be programmed.
3. SRD = Data read from status register. See Table 6 for a description of the status register bits.
PD = Data to be programmed at location PA. Data is latched on the rising edge of WE# or CE# (whichever goes high first).
ID = Data read from identifier codes.
4. Following the Read Identifier Codes command, read operations access manufacturer, device, block lock, and master lock
codes. See Section 4.2 for read identifier code data.
5. If the block is locked, RP# must be at V
HH
to enable block erase or program operations. Attempts to issue a block erase or
program to a locked block while RP# is V
IH
will fail.
6. Either 40H or 10H are recognized by the WSM as the program setup.
7. If the master lock-bit is set, RP# must be at V
to set a block lock-bit. RP# must be at V
HH
to set the master lock-bit. If the
master lock-bit is not set, a block lock-bit can be set while RP# is V
IH
.
8. If the master lock-bit is set, RP# must be at V
to clear block lock-bits. The clear block lock-bits operation simultaneously
clears all block lock-bits. If the master lock-bit is not set, the Clear Block Lock-Bits command can be done while RP# is V
IH
.
9. Commands other than those shown above are reserved by Intel for future device implementations and should not be used.
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