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參數(shù)資料
| 型號： | TDC2302B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-3/STM-1 Line Interface(STS-3/STM-1線性接口) |
| 中文描述： | STS-3/STM-1線路接口（STS-3/STM-1線性接口） |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 390K |
| 代理商： | TDC2302B |
TDC2302B
STS-3/STM-1 LINE INTERFACE
SDNS002 – SEPTEMBER 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
9
timing requirements (see Figures 3 and 4) (continued)
MIN
NOM
MAX
UNIT
tw(TXBC)H
tw(TXBC)L
tc(TXBC)
tsu(TXBD)1
th(TXBD)1
tsu(TXF)1
th(TXF)1
Pulse duration, TXBC high
18
ns
Pulse duration, TXBC low
18
ns
Clock cycle time, TXBC
Setup time, TXBD before TXBC
↓
Hold time, TXBD after TXBC
↓
Setup time, TXF before TXBC
↓
Hold time. TXF before TXBC
↓
51.44
ns
5
ns
5
ns
5
ns
5
ns
TXBDn
TXBC
ìììì
ìììì
ìììì
ìììì
ìììì
ìììì
ìììì
ìììì
ìììì
tsu(TXBD)1
th(TXBD)1
tw(TXBC)H
tw(TXBC)L
tc(TXBC)
28
28
C1
C1
TXF
Figure 3. Terminal-Side Byte Input (TPINV low)
MIN
NOM
MAX
UNIT
tw(TXBC)H
tw(TXBC)L
tc(TXBC)
tsu(TXBD)2
th(TXBD)2
tsu(TXF)2
th(TXF)2
Pulse duration, TXBC high
18
ns
Pulse duration, TXBC low
18
ns
Clock cycle time, TXBC
Setup time, TXBD before TXBC
↑
Hold time, TXBD after TXBC
↑
Setup time, TXF before TXBC
↑
Hold time, TXF after TXBC
↑
51.44
ns
5
ns
5
ns
5
ns
5
ns
TXBDn
TXBC
ìììììììììììììììììììììì
ìììììììììììììììì
tsu(TXF)2
ììììììììììì
tw(TXBC)H
tw(TXBC)L
tc(TXBC)
th(TXF)2
28
28
C1
C1
TXF
Figure 4. Terminal-Side Byte Input (TPINV high)
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