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參數(shù)資料
| 型號(hào)： | TDC2302B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-3/STM-1 Line Interface(STS-3/STM-1線性接口) |
| 中文描述： | STS-3/STM-1線路接口（STS-3/STM-1線性接口） |
| 文件頁(yè)數(shù)： | 11/17頁(yè) |
| 文件大?。?/td> | 390K |
| 代理商： | TDC2302B |
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TDC2302B
STS-3/STM-1 LINE INTERFACE
SDNS002 – SEPTEMBER 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
11
timing requirements (see Figures 7 and 8) (continued)
MIN
NOM
MAX
UNIT
tw(TXBC)H
tw(TXBC)L
tc(TXBC)
tsu(TXBD)4
th(TXBD)4
tsu(TXF)4
th(TXF)4
Pulse duration, TXBC high
9
ns
Pulse duration, TXBC low
9
ns
Clock cycle time, TXBC
Setup time, TXBD before TXBC
↑
Hold time, TXBD after TXBC
↑
Setup time, TXF before TXBC
↑
Hold time, TXF before TXBC
↑
25.72
ns
5
ns
5
ns
5
ns
5
ns
TXBDn
TXBC
tw(TXBC)L
tc(TXBC)
28
28
C1
TXF
MSB
Nibble
LSB
Nibble
tw(TXBC)H
tsu(TXBD)4
th(TXBD)4
tsu(TXF)4
th(TXF)4
Figure 7. Terminal-Side Nibble Input (TPINV high)
MIN
NOM
MAX
UNIT
tw(TXRF)L
tw(TXRC)H
tw(TXRC)L
tc(TXRC)
td(TXRF)
Pulse duration, TXRF low
51.44
ns
Pulse duration, TXRC high
23
ns
Pulse duration, TXRC low
23
ns
Clock cycle time, TXRC
Delay time, TXRF
↓
after TXRC
↑
51.44
ns
0
6
ns
TXRC
tw(TXRC)H
tw(TXRC)L
tc(TXRC)
tw(TXRF)L
td(TXRF)
TXRF
Figure 8. Terminal-Side Byte Reference Signals Output (TPINV Low)
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