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參數(shù)資料
| 型號(hào)： | TDC2302B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-3/STM-1 Line Interface(STS-3/STM-1線(xiàn)性接口) |
| 中文描述： | STS-3/STM-1線(xiàn)路接口（STS-3/STM-1線(xiàn)性接口） |
| 文件頁(yè)數(shù)： | 8/17頁(yè) |
| 文件大小： | 390K |
| 代理商： | TDC2302B |
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TDC2302B
STS-3/STM-1 LINE INTERFACE
SDNS002 – SEPTEMBER 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
8
timing requirements (see Figures 1 and 2)
All timing intervals are measured at (V
OH
– V
OL
)/2 or (V
IH
– V
IL
)/2 as applicable. TTL/CMOS outputs have a load
capacitance of C
L
= 25 pF. PECL outputs are terminated with 50
to 3 V.
MIN
NOM
MAX
UNIT
tw(RXSC)H
tw(RXSC)L
tc(RXSC)
tsu(RXSD)
th(RXSD)
Pulse duration, RXSC high
2.9
ns
Pulse duration, RXSC low
2.9
ns
Clock cycle time, RXSC
Setup time, RXSD before RXSC
↑
Hold time, RXSD after RXSC
↑
6.43
ns
3
ns
1
ns
RXSD
RXSC
ìììì
ìììì
ìììì
ìììì
ììì
ììì
Figure 1. Line-Side Input Clock and Data
tsu(RXSD)
th(RXSD)
tw(RXSC)H
tw(RXSC)L
tC(RXSC)
MIN
NOM
MAX
UNIT
tw(RXF)
tw(RXBC)H
tw(RXBC)L
tc(RXBC)
td(RXBD)
td(RXF)
Pulse duration, RXF
51.44
ns
Pulse duration, RXBC high
23
ns
Pulse duration, RXBC low
23
ns
Clock cycle time, RXBC
Delay time, RXBD after RXBC
↓
Delay time, RXF
↑
after RXBC
↓
51.44
ns
–1
6
ns
0
6
ns
C1
28
28
28
F6
tw(RXF)
td(RXF)
tw(RXBC)H
tw(RXBC)L
td(RXBD)
RXF
RXBDn
RXBC
Figure 2. Terminal-Side Byte Output
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