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參數(shù)資料
| 型號(hào)： | TDC2302B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-3/STM-1 Line Interface(STS-3/STM-1線性接口) |
| 中文描述： | STS-3/STM-1線路接口（STS-3/STM-1線性接口） |
| 文件頁(yè)數(shù)： | 14/17頁(yè) |
| 文件大?。?/td> | 390K |
| 代理商： | TDC2302B |
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TDC2302B
STS-3/STM-1 LINE INTERFACE
SDNS002 – SEPTEMBER 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
14
timing requirements (see Figures 14 and 15) (continued)
MIN
MAX
UNIT
td(TXRC)R
td(TXRF)
tw(RESET)
Delay time, TXRC after RESET
↑
Delay time, TXRF
↑
after TXRC
↑
Pulse duration, RESET
6
30
ns
0
6
ns
105
ns
TXRC
ìììììììììì
ìììììììììì
ìììììììììì
td(TXRC)R
RESET
td(TXRF)
TXRF
Figure 14. RESET Effect of Reference Clock and Frame (TPINV hIgh)
MIN
MAX
UNIT
td(RXBD)
td(B1E)
Delay time, RXBD after RXBC
↓
Delay time, B1ERR
↓
after RXBC
↓
0
6
ns
0
6
ns
td(B1E)
td(RXBD)
B1ERR
RXBDn
RXBC
Last Data Byte/Nibble
of the First Row of the
Payload
B1 Byte
Bit Error
B1 Parity Bit 7
Bit O.K.
B1 Parity Bit 6
Bit Error
B1 Parity Bit 5
Bit O.K.
B1 Parity Bit 4
NOTE: Four time slots of B1ERR output are shown; up to eight bits may be in error in a given frame.
Figure 15. B1 Error Pulse Timing – Byte Mode
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