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參數(shù)資料
| 型號： | TDC2302B |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STS-3/STM-1 Line Interface(STS-3/STM-1線性接口) |
| 中文描述： | STS-3/STM-1線路接口（STS-3/STM-1線性接口） |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 390K |
| 代理商： | TDC2302B |
TDC2302B
STS-3/STM-1 LINE INTERFACE
SDNS002 – SEPTEMBER 1992 – REVISED JUNE 1993
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
4
description (continued)
byte/nibble data input to serial data output
Nibble or byte data is clocked into the TDC2302B on negative transitions of the data input clock (TXBC). If nibble
mode is selected, the data is input using the TXBD3–TXBD0 pins with TXBD3 being the most significant bit.
If byte mode is selected, the data is input using the TXBD7–TXBD0 pins with TXBD7 being the most significant
bit. For a given byte, the most significant bit is transmitted first on the serial data output. If the scrambling and
B1 parity generation functions are to be performed by the SYNC155, then a framing pulse (TXF) identifying the
location of the third A2 byte in the incoming data is required. To facilitate the generation of TXBC and TXF, the
TDC2302B provides a reference byte or nibble clock (TXRC) and a reference frame (TXRF) output that are
generated from the 155.52-MHz clock inputs (HSCKT and HSCKC). TXRF is active low, has a nominal width
of 51.44 ns, and occurs at the frame rate of 8 KHz. TXRC occurs at a rate of 19.44 MHz or 38.88 MHz depending
upon the state of the NIB input.
The byte/nibble input data can be looped back to the byte/nibble output data if the terminal loopback (TLB) input
is high. When terminal loopback is selected, the byte/nibble input data is passed to the line-side serial data
output as well as looped back to the terminal-side output. The received line data is blocked by the looped signal
and ignored.
The byte/nibble data is scrambled and the B1 parity byte is generated if the BSCRM input is high. If the BSCRM
input is low, then these functions are bypassed. The byte/nibble data is converted to serial format and output
via TXSC, the serial output clock.
Terminal Functions
PIN
I/O
TYPE
DESCRIPTION
NAME
NO.
BSCRM
33
I
(TTL)
B1 scramble. A high on this input selects B1 parity generation/checking and scrambling/
descrambllng on both the received and transmitted signals.
B1ERR
4
O
(CMOS)
B1 parity error. This output provides a positive pulse for each B1 bit in error clocked out with the
RXBC receive clock. Each pulse is one byte-clock long.
FLB
2
I
(TTL)
Facility loopback. When this input is high, the serial input data is looped backed to the serial
output. The received serial data is also passed to the terminal output.
GND
5, 7, 8, 11, 12,
18, 25, 43, 46, 53
Digital ground (0-V reference)
HSCKC
71
I
(PECL)
High-speed clock complement. Used with HSCKT to provide a differential input clock.
HSCKT
69
I
(PECL)
High-speed clock true. Used in conjunction with the HSCKC to provide the 155.52-MHz
reference and transmit clock.
LOF
28
O
(CMOS)
Loss of frame. This output goes high whenever the OOF output is high for 24 frames. It remains
high until eight consecutive error-free frames are received.
LOS
30
O
(TTL)
Loss of signal. This output goes high whenever the receive pseudo-ECL clock or data remains
high or low for 25
±
5 ms.
This input selects either the tracking (MODE = 0) or the nontracking (MODE = 1) mode of
operation. In tracking mode, the RFE, OOF, and LOF indicators are active; in nontracking mode,
they are not.
MODE
6
I
(TTL)
NC
56, 62, 63, 67, 74
No connection
NIB
51
I
(TTL)
Nibble/byte control. If the NIB input is high, the terminal interface is nibble wide; if the NIB input
is low, the terminal interface is byte wide.
OOF
27
O
(CMOS)
Out of frame. This output goes high whenever four consecutive frames have framing errors and
remains high for at least two frames to verify timing.
OOFN
3
I
(CMOS)
Out-of-frame negative. A low-level signal on this input for two RXBC clock periods starts a new
frame search.
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