參數(shù)資料
型號: TDA9112
廠商: STMICROELECTRONICS
元件分類: 偏轉(zhuǎn)
英文描述: HORIZ/VERT DEFLECTION IC, PDIP32
封裝: PLASTIC, SDIP-32
文件頁數(shù): 9/51頁
文件大?。?/td> 809K
代理商: TDA9112
TDA9112
17/51
6.8 - DC/DC CONTROLLER SECTION
VCC = 12V, Tamb = 25°C
Note 41: A current sink is provided by the BComp output while BOut is disabled.
Note 42: Internal reference related to VRefO. The same values to be found on pin BRegIn, while regulation loop is
stabilized.
Note 43: External sawtooth configuration is assumed for V(BIsense)VThrBIsConf, internal sawtooth configuration for
V(BIsense)>VThrBIsConf.
Note 44: Only applies to configuration specified in "Test conditions" column, i.e. synchronization of BOut “Off-to-On”
edge with horizontal flyback signal. Refer to chapter "DC/DC controller" for more details.
Symbol
Parameter
Test Conditions
Value
Units
Min.
Typ.
Max.
RB+FB
Ext. resistance applied between
BComp output and BRegIn input
5k
AOLG
Open loop gain of error amplifier on
BRegIn input
Low frequency(18)
100
dB
fUGBW
Unity gain bandwidth of error amplifier
on BRegIn input
(18)
6MHz
IRI
Bias current delivered by regulation in-
put BRegIn
-0.2
A
IBComp
Output current capability of BComp out-
put.
HBOutEn = "Enable"
HBOutEn = "Disable" (41)
-0.5
0.5
2.0
mA
ABIsense
Voltage gain on BISense input
3
VThrBIsCurr
Threshold voltage on BISense input cor-
responding to current limitation
1.98
2.1
2.22
V
IBIsense
Input current sourced by BISense input
-1
A
tBOn
Conduction time of the power transistor
TH -tHVD-Hflat
IBOut
Output current capability of BOut output
0
10
mA
VBOSat
Saturation voltage of the internal output
transistor on BOut
IBOut=10mA
0.25
0.4
V
VBReg
Regulation reference for BRegIn volt-
age(42)
VRefO=8V
BREF (Sad03):
x0000000b
x1000000b
x1111111b
3.65
4.65
5.65
3.85
4.9
5.9
4.05
5.15
6.15
V
VThrBIsConf
Threshold on pin BISense to define the
DC/DC controller configuration(43)
VRefO=8V
6
V
tBTrigDel /TH
Delay of BOut “Off-to-On” edge after
middle of flyback pulse, as part of TH
(44)
V(BIsense)≤VThrBIsConf
BOutPh = "0"
16
%
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