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參數(shù)資料
| 型號： | TDA9112 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 25/51頁 |
| 文件大?。?/td> | 809K |
| 代理商： | TDA9112 |
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TDA9112
31/51
rabolas of 4th order for corner corrections inde-
pendently at the top and at the bottom) are gener-
ated from the output vertical deflection drive wave-
form, they all track with real vertical amplitude and
position (including breathing compensation), thus
being fixed on the screen. Refer to I2C BUS CON-
TROL REGISTER MAP for details on I2C bus con-
trols.
Figure 7. Horizontal timing diagram
Figure 8. HFly input configuration
9.3.6 - Output Section
The H-drive signal is inhibited (high level) during
flyback pulse, and also when VCC is too low, when
X-ray protection is activated (XRayAlarm I2C bus
flag set to 1) and when I2C bus bit HBOutEn is set
to 0 (default position).
The duty cycle of the H-drive signal is controlled
via I2C bus register
HDUTY. This is overruled dur-
ing soft-start and soft-stop procedures (see sub
chapter Soft-start and soft-stop on H-drive on
page 31 and Figure 10).
The PLL2 is followed by a rapid phase shifting
which accepts the signal from H-moiré canceller
(see sub chapter Horizontal moiré cancellation on
page 31)
The output stage consists of a NPN bipolar tran-
sistor, the collector of which is routed to HOut pin
(see Figure 9).
Figure 9. HOut configuration
Non-conductive state of HOT (Horizontal Output
Transistor) must correspond to non-conductive
state of the device output transistor.
9.3.7 - Soft-start and soft-stop on H-drive
The soft-start and soft-stop procedure is carried
out at each switch-on or switch-off of the H-drive
signal, either via HBOutEn I2C bus bit or after re-
set of XRayAlarm I2C bus flag, to protect external
power components. By its second function, the ex-
ternal capacitor on pin HPosF is used to time out
this procedure, during which the duty cycle of H-
drive signal starts at its maximum (“tHoff/TH for soft
start/stop” in electrical specifications) and slowly
decreases to the value determined by the control
I2C bus register
HDUTY (vice versa at soft-stop).
This is controlled by voltage on pin HPosF. See
Figure 10 and sub chapter Safety functions on
page 39.
9.3.8 - Horizontal moiré cancellation
The horizontal moiré canceller is intended to blur a
potential beat between the horizontal video pixel
period and the CRT pixel width, which causes vis-
ible moiré patterns in the picture.
It introduces a microscopic indent on horizontal
scan lines by injecting little controlled phase shifts
to output circuitry of the horizontal section. Their
amplitude is adjustable through
HMOIRE I2C bus
control.
The behaviour of horizontal moiré is to be opti-
mised for different deflection design configurations
using HMoiré I2C bus bit. This bit is to be kept at 0
00000
H-flyback
PLL2
H-drive
current
VThrHFly
control
+
-
(on HOut)
tS
tHoff
H-drive
region
H-drive
region
tph(max)
inhibited
tS: HOT storage time
H-Osc
VS(0)
7/8TH
TH
VHOThrHi
max.
med.
min.
VHPosF
H-sync
(polarized)
REF1
tHph
min
max
(I2C)
max.
med.
min.
PLL1 lock
(internal)
VHOThrLo
(VCO)
P
LL2
PLL1
control
ON
forced high
000000000000000000000000000000000000000000
forced low
OFF
ON
0
GND
~20k
HFly 12
~500
int.
ext.
00
26
int.
ext.
HOut
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