參數(shù)資料
型號(hào)： TDA9112
廠商： STMICROELECTRONICS
元件分類(lèi)： 偏轉(zhuǎn)
英文描述： HORIZ/VERT DEFLECTION IC, PDIP32
封裝： PLASTIC, SDIP-32
文件頁(yè)數(shù)： 3/51頁(yè)
文件大?。?/td> 809K
代理商： TDA9112
TDA9112
11/51
Note 1: Frequency at no sync signal condition. For correct operation, the frequency of the sync signal applied must
always be higher than the free-running frequency. The application must consider the spread of values of real
electrical components in RRO and CCO positions so as to always meet this condition. The formula to calculate
the free-running frequency is fHO(0)=0.12125/(RRO CCO)
Note 2: Base of NPN transistor with emitter to ground is internally connected on pin HFly through a series resistance of
about 500
and a resistance to ground of about 20k.
Note 3: Evaluated and figured out during the device qualification phase. Informative. Not tested on every single unit.
Note 4: This capture range can be enlarged by external circuitry.
Note 5: The voltage on HPLL2C pin corresponds to immediate phase of leading edge of H-drive signal on HOut pin with
respect to internal horizontal oscillator sawtooth. It must be between the two clamping levels given. Voltage
equal to one of the clamping values indicates a marginal operation of PLL2 or non-locked state.
Note 6: Internal threshold. See Figure 6.
Note 7: The tph(min)/TH parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this minimum must be increased by maximum of the total dynamic phase required
in the direction leading to bending of corners to the left. Marginal situation is indicated by reach of VTopHPLL2C
high clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
Note 8: The tph(max)/TH parameter is fixed by the application. For correct operation of asymmetry corrections through
dynamic phase modulation, this maximum must be reduced by maximum of the total dynamic phase required in
the direction leading to bending of corners to the right. Marginal situation is indicated by reach of VBotHPLL2C
low clamping level by waveform on pin HPLL2C. Also refer to Note 5 and Figure 6.
Note 9: All other dynamic phase corrections of picture asymmetry set to their neutral (medium) positions.
tPCAC/TH
Contribution of pin cushion asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
PCAC (Sad11h) full span
(9)
VPOS
at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
±1.0
±1.8
±2.8
%
tParalC/TH
Contribution of parallelogram correction
to phase of H-drive vs. static phase (via
PLL2), measured in corners
PARAL (Sad12h) full span
(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
VPOS at max. or min.
VSIZE at minimum
±1.75
±2.2
±2.8
±1.75
%
tTCAC/TH
Contribution of top corner asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
TCAC (Sad13h) full
span(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
±0.8
±2.0
±4.4
%
tBCAC/TH
Contribution of bottom corner asymmetry
correction to phase of H-drive vs. static
phase (via PLL2), measured in corners
BCAC (Sad14h) full
span(9)
VPOS at medium
VSIZE at minimum
VSIZE at medium
VSIZE at maximum
±0.8
±2.0
±4.4
%
Symbol
Parameter
Test Conditions
Value
Units
Min.
Typ.
Max.
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