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參數(shù)資料
| 型號(hào)： | TDA9112 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 偏轉(zhuǎn) |
| 英文描述： | HORIZ/VERT DEFLECTION IC, PDIP32 |
| 封裝： | PLASTIC, SDIP-32 |
| 文件頁數(shù)： | 27/51頁 |
| 文件大?。?/td> | 809K |
| 代理商： | TDA9112 |
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TDA9112
33/51
The frequency range in which the AGC loop can
regulate the amplitude also depends on this ca-
pacitor.
The C- and S-corrections of shape serve to com-
pensate for the vertical deflection system non-line-
arity. They are controlled via
CCOR and SCOR
I2C bus controls.
Shape-corrected sawtooth with regulated ampli-
tude is lead to amplitude control stage. The dis-
charge exponential is replaced by VVOB level,
which, under control of the CONTROLLER, cre-
ates a rapid falling edge and a flat part before be-
ginning of new ramp. DC value of the waveform
output on pin VOut is adjusted by means of
VPOS
I2C bus control, its amplitude through
VSIZE I2C
bus control. Vertical moiré is superimposed.
The biasing voltage for external DC-coupled verti-
cal power amplifier is to be derived from VRefO
voltage provided on pin RefOut, using a resistor di-
vider, this to ensure the same temperature drift of
mean (DC) levels on both differential inputs and to
compensate for spread of VRefO value (and so
mean output value) between particular devices.
9.4.2 - Vertical moiré
To blur the interaction of deflection lines with CRT
mask grid pitch that can generate moiré pattern,
the picture position is to be alternated at frame fre-
quency. For this purpose, a square waveform at
half-frame frequency is superimposed on the out-
put waveform’s DC value. Its amplitude is adjusta-
ble through
VMOIRE I2C bus control.
Figure 11. Vertical section block diagram
9.5 - EW DRIVE SECTION
The goal of the EW drive section is to provide, on
pin EWOut, a waveform which, used by an exter-
nal DC-coupled power stage, serves to compen-
sate for those geometry errors of the picture that
are symmetric versus vertical axis across the mid-
dle of the picture.
The waveform consists of an adjustable DC value,
corresponding to horizontal size, a parabola of 2nd
order for “pin cushion” correction, a linear for “key-
stone” correction and independent half-parabolas
of 4th order for top and bottom corner corrections.
All of them are adjustable via I2C bus, see I2C
BUS CONTROL REGISTER MAP chapter.
Refer to Figure 12, Figure 13 and to chapter TYP-
ICAL OUTPUT WAVEFORMS. The correction
2
Synchro
Polarity
Controller
Discharge
22
Sampling
Capacitance
S-correction
CCOR
C-correction
18
23
VVOB
sawtooth
REF
Charge current
Transconductance amplifier
(I2C)
SCOR (I2C)
20 VAGCCap
discharge
CCOR
VSIZE (I2C)
VMOIRE (I2C)
VPOS (I2C)
19
VOscF
VOut
VEHTIn
VCap
VSyn
OSC
Cap.
Q1
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