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參數(shù)資料
| 型號： | TDA8779 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 10-bit converter interface ADC/DAC for quadrature transceiver |
| 中文描述： | 10位ADC的轉(zhuǎn)換接口/ DAC的收發(fā)器的正交 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大小： | 149K |
| 代理商： | TDA8779 |
1996 Sep 18
9
Philips Semiconductors
Objective specification
10-bit converter interface (ADC/DAC) for
quadrature transceiver
TDA8779
S
TANDBY MODE OUTPUT DELAY TIMES
; STDBYA
t
d(stb)LH
t
d(stb)HL
C
ROSSTALK ON THE
ADC
α
ct
crosstalk into the ADC
standby (LOW-to-HIGH transition)
start-up (HIGH-to-LOW transition)
100
100
μ
s
μ
s
f
CLK(DAC)
= 16.384 MHz;
f
CLK(ADC)
= 8.192 MHz;
T
amb
= 25
°
C; both DACs
switching between input
codes 0 and 1023; one
ADC 1 V (p-p) sine wave at
4 MHz and the other ADC
set at the middle code
55
dB
DAC PART
D
IGITAL INPUTS
: D0D
TO
D9D
AND
CLKD
V
IL
V
IH
I
IL
I
IH
D
IGITAL INPUT
; STDBYD
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
0
2.2
200
10
120
0.6
V
CCD2
V
0
+10
V
μ
A
μ
A
V
IL
V
IH
I
IL
I
IH
T
IMING
: see Fig.5
LOW level input voltage
HIGH level input voltage
LOW level input current
HIGH level input current
0
2.2
1
0
0.6
V
CCD2
V
+1
1
V
μ
A
μ
A
f
CLK(max)
t
CH
t
CL
t
r
t
f
t
s
t
h
A
NALOG OUTPUTS
; note 1
maximum clock frequency
clock pulse width HIGH
clock pulse width LOW
clock rise time
clock fall time
input data set-up time
input data hold time
20
20
20
10
0
4
4
tbf
tbf
MHz
ns
ns
ns
ns
ns
ns
V
o(p-p)
Z
oL
output voltage (peak-to-peak value)
output load impedance
full-scale
see Fig.6
tbf
1
15
0.3
tbf
V
pF
k
T
RANSFER FUNCTION
INLD
DNLD
B
integral non linearity
differential non linearity
maximum bandwidth
ramp input; f
CLK
= 20 MHz
ramp input; f
CLK
= 20 MHz;
full scale; T
amb
= 25
°
C
5.5
±
3
±
0.75
LSB
LSB
MHz
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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