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參數(shù)資料
| 型號： | TDA8779 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 10-bit converter interface ADC/DAC for quadrature transceiver |
| 中文描述： | 10位ADC的轉(zhuǎn)換接口/ DAC的收發(fā)器的正交 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 149K |
| 代理商： | TDA8779 |
1996 Sep 18
2
Philips Semiconductors
Objective specification
10-bit converter interface (ADC/DAC) for
quadrature transceiver
TDA8779
FEATURES
Two 10-bit ADCs with multiplexed outputs
Two 10-bit DACs with multiplexed inputs
Sampling rate for the ADCs and DACs up to 20 MHz
Digital outputs (for the ADC) and inputs (for the DAC)
are TTL/CMOS compatible (2.7 to 5.5 V)
Internal reference voltage regulator
Power dissipation 520 mW
Standby mode.
APPLICATIONS
Wireless communication.
GENERAL DESCRIPTION
The TDA8779 contains two 10-bit high speed ADCs and
two 10-bit DACs for wireless communication (for use in
transceiver modules). This device converts two analog
input signals (channels I and Q) and digital inputs
(D0 to D9) at a maximum sampling rate of 20 MHz.
The input bias voltages for the analog input voltages are
provided internally at the middle code. The analog input
and output voltages are AC coupled.
The data sampling is performed on the rising edge of the
clock for ADCs and DACs.
All reference voltages are generated internally.
QUICK REFERENCE DATA
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
V
CCA1
analog supply voltage for the
ADC part
digital supply voltage for the
ADC part
analog supply voltage for the
DAC part
digital supply voltage for the
DAC part
output stage supply voltage
analog supply current
digital supply current
output stage supply current
maximum clock frequency for
the ADC part
integral non linearity for the
ADC part
differential non linearity for
the ADC part
maximum clock frequency for
the DAC part
integral non linearity for the
DAC part
differential non linearity for
the DAC part
total power dissipation
4.75
5.0
5.5
V
V
CCD1
4.75
5.0
5.5
V
V
CCA2
4.75
5.0
5.5
V
V
CCD2
4.75
5.0
5.5
V
V
CCO
I
CCA
I
CCD
I
CCO
f
CLK(ADC)max
2.7
20
3.0
71
31
2
5.5
V
mA
mA
mA
MHz
ramp input; f
CLK
= 20 MHz
INLA
full-scale; ramp input;
f
CLK
= 20 MHz
50% full-scale; ramp input;
f
CLK
= 20 MHz
±
2
LSB
DNLA
±
0.3
LSB
f
CLK(DAC)max
20
MHz
INLD
full-scale; ramp input;
f
CLK
= 20 MHz
full-scale; ramp input;
f
CLK
= 20 MHz
±
2
LSB
DNLD
±
0.75
LSB
P
tot
520
mW
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