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參數(shù)資料
| 型號： | TDA8779 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | 10-bit converter interface ADC/DAC for quadrature transceiver |
| 中文描述： | 10位ADC的轉(zhuǎn)換接口/ DAC的收發(fā)器的正交 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大小： | 149K |
| 代理商： | TDA8779 |
1996 Sep 18
8
Philips Semiconductors
Objective specification
10-bit converter interface (ADC/DAC) for
quadrature transceiver
TDA8779
A
NALOG SIGNAL PROCESSING
Linearity
INLA
DNLA
integral non linearity
differential non linearity
ramp input; f
CLK
= 20 MHz
full-scale; ramp input;
f
CLK
= 20 MHz
50% full-scale; ramp input;
f
CLK
= 20 MHz
±
2
0.5
LSB
LSB
±
0.3
LSB
Noise floor; note 2
NF
noise floor
f
in
= 5.1 MHz; 20 Msps
60
dB
Harmonics; note 3
THD
total harmonic distortion
f
i
= 5.1 MHz; 20 Msps
54
dB
Spurious free dynamic range
SFDR
spurious free dynamic range
f
i
= 5.1 MHz; 20 Msps
45
56
dB
Matching between the I and Q channels
V
amplitude matching
f
in
= 5.1 MHz;
f
CLK
= 20 MHz;
T
amb
= 25
°
C
f
in
= 5.1 MHz;
f
CLK
= 20 MHz;
T
amb
= 25
°
C
6
%
phase matching
2
Deg
Bandwidth
B
bandwidth maximum attenuation of
0.3 dB
full-scale sine wave;
T
amb
= 25
°
C;
50% full-scale sine wave;
T
amb
= 25
°
C;
5.5
MHz
tbf
MHz
T
IMING
: (
THE OUTPUT DATA IS AVAILABLE AFTER THE MAXIMUM DELAY TIME
t
d
); C
L
= 15 pF; see Fig.3
t
ds
sampling delay time
t
h
output hold time
t
d
output delay time
5
12
17
21
5
15
20
24
ns
ns
ns
ns
ns
V
CCO
= 4.75 V
V
CCO
= 3.15 V
V
CCO
= 2.7 V
3-
STATE OUTPUT DELAY TIMES
; see Fig.4
t
dZH
t
dZL
t
dHZ
t
dLZ
output delay enable HIGH
output delay enable LOW
output delay disable HIGH
output delay disable LOW
14
16
16
14
18
20
20
18
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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