參數(shù)資料
型號(hào)： TDA8769
廠商： NXP Semiconductors N.V.
英文描述： 12-bit, 60/80/105 Msps Analog-to-Digital Converter (ADC) Nyquist/high IF sampling
中文描述： 12位，60/80/105 Msps的模擬到數(shù)字轉(zhuǎn)換器（ADC）奈奎斯特/ IF采樣高
文件頁(yè)數(shù)： 9/28頁(yè)
文件大?。?/td> 217K
代理商： TDA8769
2003 Dec 09
9
Philips Semiconductors
Objective specification
12-bit, 60/80/105 Msps Analog-to-Digital Converter
(ADC) Nyquist/high IF sampling
TDA8769
Reference voltage input: pin VREF;
note 3
V
ref(FS)
full-scale fixed
voltage
input voltage
(peak-to-peak
value)
input current
f
i
= 25 MHz;
f
CLK
= 105 Msps
V
i
= V
IN
V
INN
;
V
VREF
= V
CCA3
1.75 V;
V
i(CM)
= V
CCA3
1.6 V
V
CCA3
1.75
V
V
i(p-p)
1.9
V
I
ref
Full-scale voltage controlled regulator output: pin FSREF
0.3
10
μ
A
V
o(FS)
1.9 V full-scale
output voltage
load current
V
CCA3
1.75
V
I
L(FS)
Digital outputs: pins D11 to D0 and IR
1
2
mA
O
UTPUT LEVELS
V
OL
LOW-level
output voltage
HIGH-level
output voltage
output current in
3-state
I
OL
= 2 mA
DGND
DGND + 0.5 V
V
OH
I
OH
=
0.4 mA
V
CCO
0.5
V
CCO
V
I
OZ
output level between
0.5 V and V
CCO
20
+20
μ
A
T
IMING
; see Fig. 3
t
d(s)
t
h(o)
t
d(o)
3-
STATE OUTPUT DELAY
sampling delay
output hold time
output delay
C
L
= 10 pF; note 4
C
L
= 10 pF
C
L
= 10 pF
(tbf)
(tbf)
3.7
4.6
(tbf)
(tbf)
ns
ns
ns
t
dZH
enable to HIGH
state
enable to LOW
state
disable from
HIGH state
disable from
LOW state
2.8
ns
t
dZL
7.5
ns
t
dHZ
7.2
ns
t
dLZ
2.9
ns
Timing complete conversion signal: pin CCS
t
d(CCS)
complete
conversion
signal delay
C
L
= 10 pF; see Table 4
and Fig 4
DEL0 = LOW;
DEL1 = HIGH
DEL0 = HIGH;
DEL1 = LOW
DEL0 = HIGH;
DEL1 = HIGH
0
ns
1.2
ns
2.2
ns
SYMBOL
PARAMETER
CONDITIONS
TEST
(1)
MIN.
TYP.
MAX.
UNIT
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