參數(shù)資料
型號: TC1300
廠商: Microchip Technology Inc.
元件分類: 基準電壓源/電流源
英文描述: 300 mA CMOS LDO with Shutdown, Bypass and Independent Delayed Reset Function
中文描述: 300毫安的CMOS低壓降穩(wěn)壓器,帶有關斷,繞道和獨立延遲復位功能
文件頁數(shù): 8/16頁
文件大小: 326K
代理商: TC1300
TC1300
DS21385C-page 8
2002 Microchip Technology Inc.
3.0
DETAILED DESCRIPTION
The TC1300 is a combination of a fixed output, low
dropout
regulator
and
monitor/RESET. Unlike bipolar regulators, the TC1300
supply current does not increase with load current. In
addition, V
OUT
remains stable and within regulation
over the entire specified operating load range (0 mA to
300 mA) and operating input voltage range (2.7V to
6.0V).
a
microcontroller
Figure 3-1 shows a typical application circuit. The reg-
ulator is enabled any time the shutdown input (SHDN)
is above V
IH
. The regulator is shutdown (disabled)
when SHDN is at or below V
IL
. SHDN may be con-
trolled by a CMOS logic gate or an I/O port of a micro-
controller. If the SHDN input is not required, it should be
connected directly to the input supply. While in shut-
down, supply current decreases to 30 μA (typical),
V
OUT
falls to zero and RESET remains valid.
3.1
RESET
Output
The RESET output is driven active-low within 160 μsec
of V
DET
falling through the reset voltage threshold.
RESET is maintained active for a minimum of
140 msec after V
DET
rises above the reset threshold.
The TC1300 has an active-low RESET output. The out-
put of the TC1300 is valid down to V
DET
= 1V and is
optimized to reject fast transient glitches on the V
DET
line.
FIGURE 3-1:
Typical Application Circuit.
3.2
Output Capacitor
A 1 μF (min) capacitor from V
OUT
to ground is required.
A 1 μF capacitor should also be connected from V
IN
to
GND if there is more than 10 inches of wire between
the regulator and the AC filter capacitor, or if a battery
is used as the power source. As with all low dropout
regulators, a minimum output capacitance is required
to stabilize the output voltage. For the TC1300, a mini-
mum of 1 μF of output capacitance is enough to stabi-
lize the device over the entire operating load and line
range. The selected output capacitor plays an impor-
tant role is compensating the LDO regulator. For the
TC1300, the selected output capacitor equivalent
series resistance (ESR) range is 0.1 ohms to 5 ohms
when using 1 μF of output capacitance, and 0.01 ohms
to 5 ohms when using 10 μF of output capacitance.
Because of the ESR requirement, tantalum and alumi-
num electrolytic capacitors are recommended. Alumi-
num electrolytic capacitors are not recommended for
operation at temperatures below -25°C. When operat-
ing from sources other than batteries, rejection and
transient responses can be improved by increasing the
value of the input and output capacitors and employing
passive filtering techniques.
3.3
Bypass Input (Optional)
An optional 470 pF capacitor connected from the
Bypass input to ground reduces noise present on the
internal reference, which in turn significantly reduces
output noise and improves PSRR performance. This
input may be left unconnected. Larger capacitor values
may be used, but results in a longer time period to rated
output voltage when power is initially applied.
3.4
Turn On Response
The turn-on response is defined as two separate
response categories, Wake-Up Time (t
WK
) and Settling
Time (t
S
).
The TC1300 has a fast Wake-Up Time (10 μsec typi-
cal) when released from shutdown. See Figure 3-2 for
the Wake-Up Time designated as t
WK
. The Wake-Up
Time is defined as the time it takes for the output to rise
to 2% of the V
OUT
value after being released from
shutdown.
The total turn-on response is defined as the Settling
Time (t
S
) (see Figure 3-2). Settling Time (inclusive with
t
WK
) is defined as the condition when the output is
within 2% of its fully enabled value (50 μsec typical)
when released from shutdown. The settling time of the
output voltage is dependent on load conditions and
output capacitance on V
OUT
(RC response).
FIGURE 3-2:
Wake-Up Response Time.
TC1300
1
2
3
4
5
6
7
8
V
OUT
C
470 pF
(Optional)
Shutdown Control
(from Power
Control Logic)
GND
Bypass
V
IN
SHDN
V
OUT
C
1 μF
RESET
V
DET
NC
C
1 μF
Battery
V
DET
+
RESET
Microcontroller
V
IH
t
S
t
WK
V
OUT
98%
2%
V
IL
SHDN
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