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參數(shù)資料
| 型號(hào)： | TB2118FG |
| 廠商： | Toshiba Corporation |
| 英文描述： | High Speed PLL For DTS |
| 中文描述： | 高高速PLL為DTS |
| 文件頁數(shù)： | 6/20頁 |
| 文件大小： | 348K |
| 代理商： | TB2118FG |
TB2118FG
2006-04-12
6
Operation
1. Configuration of control data (serial data input / output)
1) Data input mode (valid data length changes according to the address.)
A
0
A
1
A
2
A
3
Input Mode
Valid Data
Length
Remarks
0
#
0
1
(1)
24bits
Processes frequency change.
0
#
1
0
(2)
32bits
Processes band change.
0
#
1
1
(3)
40bits
Processes power on (initialization).
When "0" is set in bits marked with #, data are loaded to register 1; when "1" is set, to register 2.
(Note)
●
Either "0" or "1" can be set in bits marked with *.
●
TS1 and TS2 are pins for internal testing. At power on, be sure to clear to "0" (data set).
*
*
*
*
A
3
A
0
A
1
A
2
(note)
(address)
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
C
C
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
P
C
C
Register 1
Register 2
S
O
O
*
I
I
F
F
O
I
T
I
D
T
R
0
R
1
R
2
G
A
G
O
M
Input mode (1)
Input mode (2)
Input mode (3)
(note)
●
Test bit
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