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參數(shù)資料
| 型號： | TB2118FG |
| 廠商： | Toshiba Corporation |
| 英文描述： | High Speed PLL For DTS |
| 中文描述： | 高高速PLL為DTS |
| 文件頁數(shù)： | 13/20頁 |
| 文件大?。?/td> | 348K |
| 代理商： | TB2118FG |
TB2118FG
2006-04-12
13
4) Detecting counter operating status
Busy
Counter Operating Status
Over
Counter Value
0
Counting ended
0
N
≤
2
20
1
1
Counting
1
N
≥
2
20
(overflow)
(*) Setting the DOC bit to "1" enables constant output of busy state from the D
OUT
pin.
Note that at this time, the busy status is the inversion of the busy bit: busy status = 0 (counting) and busy status =
1 (counting ended).
The DOC bit is set to "0" at power on.
5) Counter timing (when PLL data are updated and counting starts)
CE
(new data)
(old data)
Wait time
Gate time
( * ) Constant output from
D
OUT
pin enabled.
Pll data
Gate
Counter input
Busy
Over
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