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參數(shù)資料
| 型號： | TAS5000PFBG4 |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | GREEN, TQFP-48 |
| 文件頁數(shù)： | 7/25頁 |
| 文件大?。?/td> | 108K |
| 代理商： | TAS5000PFBG4 |
2–5
Table 2–4. Hardware Selection of Serial Audio Modes
MODE
MOD2 PIN
MOD1 PIN
MOD0 PIN
SERIAL INTERFACE
SDIN
0
16 bit, MSB first; right justified
1
0
1
20 bit, MSB first; right justified
2
0
1
0
24 bit, MSB first; right justified
3
0
1
16 bit IIS
4
1
0
20 bit IIS
5
1
0
1
24 bit IIS
6
1
0
16 bit MSB first, left justified
7
1
16 bit DSP frame
The following figures illustrate the relationship between the SCLK, LRCLK and the serial data I/O for the different
interface protocols. Note that there are always 64 SCLKs per LRCLK. The nondata bits are padded with binary 0.
2.8.1
MSB First Right Justified (for 16-, 20-, 24-bits)
X
MSB
LSB
X
MSB
LSB
SCLK
LRCLK = Fs
SDIN
Left Channel
Right Channel
Figure 2–6. MSB First Right Justified
Note the following characteristics of this protocol.
Left channel is received when LRCLK is high.
Right channel is received when LRCLK is low.
The SDIN data is justified to the trailing edge of the LRCLK
SDIN is sampled at the rising edge of SCLK.
If LRCLK phase changes by more than 10 MCLKs, then the chip automatically resets.
2.8.2
IIS Compatible Serial Format ( for 16-, 20-, 24-bits)
X
MSB
LSB
X
MSB
LSB
SCLK
LRCLK = Fs
SDIN
Left Channel
Right Channel
Figure 2–7. IIS Compatible Serial Format
Note the following characteristics of this protocol.
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| TAS5001IPFB | 功能描述:音頻 DSP Digital Audio PWM Processor RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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